Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 64a987d143..3b765408f2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7353,6 +7353,11 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const
ARMCPRegInfo *r)
assert(r->state == ARM_CP_STATE_AA32 || !(r->type & ARM_CP_64BIT));
/* AArch32 64-bit registers have only CRm and Opc1 fields. */
assert(!(r->type & ARM_CP_64BIT) || !(r->opc2 || r->crn));
+ /*
+ * Only AArch64 regs are 128-bit. There is usually an AArch32 64-bit
+ * alias, but must be defined separately due to encoding conflicts above.
+ */
+ assert(r->state == ARM_CP_STATE_AA64 || !(r->type & ARM_CP_128BIT));
/* op0 only exists in the AArch64 encodings */
assert(r->state != ARM_CP_STATE_AA32 || r->opc0 == 0);
--
2.43.0