On Wed, Aug 27, 2025 at 4:11 AM Richard Henderson <[email protected]> wrote: > > These pointers are no opaque, they have a specific type. > > Signed-off-by: Richard Henderson <[email protected]> > ---
Reviewed-by: Manos Pitsidianakis <[email protected]> > target/arm/cpregs.h | 10 +++++----- > target/arm/helper.c | 6 +++--- > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h > index c9506aa6d5..3344a02bd3 100644 > --- a/target/arm/cpregs.h > +++ b/target/arm/cpregs.h > @@ -841,15 +841,15 @@ typedef struct ARMCPRegInfo ARMCPRegInfo; > * Access functions for coprocessor registers. These cannot fail and > * may not raise exceptions. > */ > -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); > -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, > +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *ri); > +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value); > /* Access permission check functions for coprocessor registers. */ > typedef CPAccessResult CPAccessFn(CPUARMState *env, > - const ARMCPRegInfo *opaque, > + const ARMCPRegInfo *ri, > bool isread); > /* Hook function for register reset */ > -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); > +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *ri); > > #define CP_ANY 0xff > > @@ -1075,7 +1075,7 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo > *ri, uint64_t value); > * CPResetFn that does nothing, for use if no reset is required even > * if fieldoffset is non zero. > */ > -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); > +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); > > /* > * Return true if this reginfo struct's field in the cpu state struct > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d230f9e766..e03cbc0394 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -1067,7 +1067,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { > .resetvalue = 0 }, > }; > > -static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) > +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *ri) > { > ARMCPU *cpu = env_archcpu(env); > > @@ -5407,7 +5407,7 @@ static const ARMCPRegInfo rndr_reginfo[] = { > .access = PL0_R, .readfn = rndr_readfn }, > }; > > -static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, > +static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > #ifdef CONFIG_TCG > @@ -7730,7 +7730,7 @@ uint64_t arm_cp_read_zero(CPUARMState *env, const > ARMCPRegInfo *ri) > return 0; > } > > -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) > +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri) > { > /* Helper coprocessor reset function for do-nothing-on-reset registers */ > } > -- > 2.43.0 > >
