On 23/06/25, Daniel Henrique Barboza wrote: > Hi, > > The output of HMP 'info registers', implemented by the cpu_dump_state > callback, returns way less CSRs than what we have available in the > default rv64 CPU with default options. > > This series changes the callback to add all available non-vector CSRs > when issuing 'info registers'. The vector CSRs are being handled by > another patch [1]. > > Patches based on alistair/riscv-to-apply.next. > > [1] > https://lore.kernel.org/qemu-riscv/20250623145306.991562-1-dbarb...@ventanamicro.com/ > > > Daniel Henrique Barboza (3): > target/riscv/cpu: add riscv_dump_csr() helper > target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state() > target/riscv: print all available CSRs in riscv_cpu_dump_state() > > target/riscv/cpu.c | 107 +++++++++++++++++---------------------------- > target/riscv/cpu.h | 2 + > target/riscv/csr.c | 18 ++++++++ > 3 files changed, 61 insertions(+), 66 deletions(-) > > -- > 2.49.0 > >
I think this makes sense, less manual maintainence is always a plus!:) Series: reviewed-by: Anton Johansson <a...@rev.ng>
