On Wed, Sep 24, 2025 at 5:50 PM Jim Shu <jim....@sifive.com> wrote: > > When sspopchk is in the middle of TB and triggers the SW check > exception, it should update PC from gen_update_pc(). If not, RISC-V mepc > CSR will get wrong PC address which is still at the start of TB. > > Signed-off-by: Jim Shu <jim....@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvzicfiss.c.inc | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc > b/target/riscv/insn_trans/trans_rvzicfiss.c.inc > index b0096adcd0..45686af4d6 100644 > --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc > +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc > @@ -40,6 +40,7 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk > *a) > tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); > tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_BCFI_TVAL), > tcg_env, offsetof(CPURISCVState, sw_check_code)); > + gen_update_pc(ctx, 0); > gen_helper_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > gen_set_label(skip); > -- > 2.43.0 > >
