On 30/9/25 08:37, Luc Michel wrote:
Hi Phil,
On 12:34 Mon 29 Sep , Philippe Mathieu-Daudé wrote:
On 26/9/25 09:07, Luc Michel wrote:
Add the target field in the IRQ descriptor. This allows to target an IRQ
to another IRQ controller than the GIC(s). Other supported targets are
the PMC PPU1 CPU interrupt controller and the EAM (Error management)
device. Those two devices are currently not implemented so IRQs
targeting those will be left unconnected. This is in preparation for
versal2.
Signed-off-by: Luc Michel <[email protected]>
Reviewed-by: Francisco Iglesias <[email protected]>
Reviewed-by: Edgar E. Iglesias <[email protected]>
---
hw/arm/xlnx-versal.c | 41 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 3d960ed2636..64744401182 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -50,18 +50,30 @@
#include "hw/cpu/cluster.h"
#include "hw/arm/bsa.h"
/*
* IRQ descriptor to catch the following cases:
+ * - An IRQ can either connect to the GICs, to the PPU1 intc, or the the EAM
* - Multiple devices can connect to the same IRQ. They are OR'ed together.
*/
FIELD(VERSAL_IRQ, IRQ, 0, 16)
+FIELD(VERSAL_IRQ, TARGET, 16, 2)
FIELD(VERSAL_IRQ, ORED, 18, 1)
FIELD(VERSAL_IRQ, OR_IDX, 19, 4) /* input index on the IRQ OR gate */
+typedef enum VersalIrqTarget {
+ IRQ_TARGET_GIC,
+ IRQ_TARGET_PPU1,
+ IRQ_TARGET_EAM,
Maybe declare IRQ_TARGET_RSVD here,
I'm not convinced. In the future we may need more targets, even more
than 4. In this case we will increase the TARGET field size, probably we
will then have even more reserved fields. I feel the way it's done here
is simple enough to catch all the buggy cases thanks to the default case
in the switch below.
Fine then!
