On Fri, Oct 3, 2025 at 5:11 AM Pierrick Bouvier <[email protected]> wrote: > > On 10/1/25 12:39 AM, Philippe Mathieu-Daudé wrote: > > On 1/10/25 09:32, Anton Johansson wrote: > >> According to version 20250508 of the privileged specification, > >> mhpmeventn is 64 bits in size and mhpmeventnh is only ever used > >> when XLEN == 32 and accesses the top 32 bits of the 64-bit > >> mhpmeventn registers. Combine the two arrays of target_ulong > >> mhpmeventh[] and mhpmevent[] to a single array of uint64_t. > >> > >> This also allows for some minor code simplification where branches > >> handling either mhpmeventh[] or mhpmevent[] could be combined. > >> > >> Signed-off-by: Anton Johansson <[email protected]> > >> --- > >> target/riscv/cpu.h | 10 +++---- > >> target/riscv/csr.c | 67 +++++++++++++++--------------------------- > >> target/riscv/machine.c | 3 +- > >> target/riscv/pmu.c | 53 ++++++++------------------------- > >> 4 files changed, 42 insertions(+), 91 deletions(-) > > > > > >> diff --git a/target/riscv/machine.c b/target/riscv/machine.c > >> index 328fb674e1..d9939489e1 100644 > >> --- a/target/riscv/machine.c > >> +++ b/target/riscv/machine.c > >> @@ -452,8 +452,7 @@ const VMStateDescription vmstate_riscv_cpu = { > >> VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), > >> VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, > >> RV_MAX_MHPMCOUNTERS, 0, > >> vmstate_pmu_ctr_state, PMUCTRState), > >> - VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, > >> RV_MAX_MHPMEVENTS), > >> - VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, > >> RV_MAX_MHPMEVENTS), > >> + VMSTATE_UINT64_ARRAY(env.mhpmevent_val, RISCVCPU, > >> RV_MAX_MHPMEVENTS), > > > > Each time you change a VMStateDescription structure you need to bump its > > version. > > Maybe we could agree with Alistair if we prefer a single bump for whole > series, or bump on any change within this series.
I'm fine with one bump in the series. Otherwise we end up with a huge number of bumps Alistair >
