On 01/10/25, Philippe Mathieu-Daudé wrote: > On 1/10/25 09:32, Anton Johansson wrote: > > gprh is only needed for TARGET_RISCV64 when modeling 128-bit registers, > > fixing their size to 64 bits makes sense. > > > > gpr is also fixed to 64 bits since all direct uses of env->gpr > > correctly zero extend/truncate to/from target_ulong, meaning > > !TARGET_RISCV64 will behave as expected. > > > > We do however need to be a bit careful when mapping 64-bit fields to > > 32-bit TCGv globals on big endian hosts. > > > > Note, the cpu/rv128 VMSTATE version is bumped, breaking migration from > > older versions. > > > > Signed-off-by: Anton Johansson <[email protected]> > > --- > > target/riscv/cpu.h | 4 ++-- > > target/riscv/cpu.c | 2 +- > > target/riscv/machine.c | 8 ++++---- > > target/riscv/translate.c | 17 +++++++++++++++-- > > 4 files changed, 22 insertions(+), 9 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index d055ddf462..3c910e44cd 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -584,7 +584,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, > > int flags) > > for (i = 0; i < 32; i++) { > > qemu_fprintf(f, " %-8s " TARGET_FMT_lx, > > - riscv_int_regnames[i], env->gpr[i]); > > + riscv_int_regnames[i], (target_ulong) env->gpr[i]); > > Rebase mistake?
Yup, I'll print as u64 instead! Thanks:)
