I will send a v3 patch to fix it, thanks! - Jim
On Sat, Aug 9, 2025 at 8:48 PM Daniel Henrique Barboza <[email protected]> wrote: > > > > On 4/17/25 7:52 AM, Jim Shu wrote: > > We define CPU options for WG CSR support in RISC-V CPUs which > > can be set by machine/device emulation. The RISC-V CSR emulation > > will also check this feature for emulating WG CSRs. > > > > Signed-off-by: Jim Shu <[email protected]> > > --- > > target/riscv/cpu.c | 3 +++ > > target/riscv/cpu_cfg.h | 3 +++ > > target/riscv/tcg/tcg-cpu.c | 11 +++++++++++ > > 3 files changed, 17 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 09ded6829a..a182e8c61f 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -236,6 +236,9 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, > > ext_xtheadmempair), > > ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), > > ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, > > ext_XVentanaCondOps), > > + ISA_EXT_DATA_ENTRY(smwg, PRIV_VERSION_1_12_0, ext_smwg), > > + ISA_EXT_DATA_ENTRY(smwgd, PRIV_VERSION_1_12_0, ext_smwgd), > > + ISA_EXT_DATA_ENTRY(sswg, PRIV_VERSION_1_12_0, ext_sswg), > > We need to keep isa_edata_arr in order because we use it to create the > riscv,isa DT: > > > $ git diff > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d055ddf462..714fff9c33 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -207,6 +207,8 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), > ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > + ISA_EXT_DATA_ENTRY(smwg, PRIV_VERSION_1_12_0, ext_smwg), > + ISA_EXT_DATA_ENTRY(smwgd, PRIV_VERSION_1_12_0, ext_smwgd), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg), > ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > @@ -222,6 +224,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_EXT_DATA_ENTRY(sswg, PRIV_VERSION_1_12_0, ext_sswg), > ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm), > ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), > > > > Thanks, > > Daniel > > > > > { }, > > }; > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > > index 8a843482cc..a5b045aa2f 100644 > > --- a/target/riscv/cpu_cfg.h > > +++ b/target/riscv/cpu_cfg.h > > @@ -143,6 +143,9 @@ struct RISCVCPUConfig { > > bool ext_smmpm; > > bool ext_sspm; > > bool ext_supm; > > + bool ext_smwg; > > + bool ext_smwgd; > > + bool ext_sswg; > > bool rvv_ta_all_1s; > > bool rvv_ma_all_1s; > > bool rvv_vl_half_avl; > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > > index 5aef9eef36..343e46e698 100644 > > --- a/target/riscv/tcg/tcg-cpu.c > > +++ b/target/riscv/tcg/tcg-cpu.c > > @@ -694,6 +694,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, > > Error **errp) > > cpu->cfg.ext_ssctr = false; > > } > > > > + /* RISC-V WorldGuard */ > > + if (cpu->cfg.ext_sswg && !cpu->cfg.ext_smwg) { > > + error_setg(errp, "Sswg extension requires Smwg extension"); > > + return; > > + } > > + > > + if (cpu->cfg.ext_smwgd != cpu->cfg.ext_sswg) { > > + error_setg(errp, "Smwgd/Sswg extensions should be enabled > > together"); > > + return; > > + } > > + > > /* > > * Disable isa extensions based on priv spec after we > > * validated and set everything we need. >
