On 10/17/25 05:49, Peter Maydell wrote:
On Tue, 14 Oct 2025 at 21:19, Richard Henderson
<[email protected]> wrote:
Do not yet produce the 128-bit AT format result, but zero the
high bits whenever the low bits are written. This corresponds
to PAR_EL1.D128 = 0, and bits [127:65] as RES0.
Signed-off-by: Richard Henderson <[email protected]>
diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c
index 0e8f229aa7..9e6af3d974 100644
--- a/target/arm/tcg/cpregs-at.c
+++ b/target/arm/tcg/cpregs-at.c
@@ -353,6 +353,7 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
ss = for_el3 ? arm_security_space(env) :
arm_security_space_below_el3(env);
env->cp15.par_el[1] = do_ats_write(env, value, access_perm, mmu_idx, ss);
+ env->cp15.par_el1_hi = 0;
}
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -496,6 +497,7 @@ static void ats_s1e1a(CPUARMState *env, const ARMCPRegInfo
*ri, uint64_t value)
ARMSecuritySpace ss = arm_security_space_below_el3(env);
env->cp15.par_el[1] = do_ats_write(env, value, 0, mmu_idx, ss);
+ env->cp15.par_el1_hi = 0;
I guess this is where the downside of not storing the
register as an Int128 shows up -- we have to remember
to explicitly clear the high half everywhere that we
have code that's doing an implicit-write to the 64-bit
version of the register.
Yes. Thankfully, PAR_EL1 is the only 128-bit register with implicit writes.
r~
