On 14/10/25 22:34, Anton Johansson wrote:
Hi,
this is a first patchset moving towards single-binary support for riscv.
Additional patchsets for hw/ and target/ are based on this one so it's
best to make sure the approach taken is ok. Most patches in this set
concern fields in CPUArchState which are either widened (usually to
uint64_t) or fixed to a smaller size which handles all use cases.
General purpose registers and fields mapped to TCG are dealt with by
widening the type and applying an offset to tcg_global_mem_new() to
correctly handle 32-bit targets on big endian hosts.
In order to not break bisectability, maybe set:
vmstate_riscv_cpu.unmigratable = 1
in the first patch, ...
target/riscv: Fix size of trivial CPUArchState fields
target/riscv: Fix size of mhartid
target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val()
target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read
target/riscv: Combine mhpmevent and mhpmeventh
target/riscv: Combine mcyclecfg and mcyclecfgh
target/riscv: Combine minstretcfg and minstretcfgh
target/riscv: Combine mhpmcounter and mhpmcounterh
target/riscv: Fix size of gpr and gprh
target/riscv: Fix size of vector CSRs
target/riscv: Fix size of pc, load_[val|res]
target/riscv: Fix size of frm and fflags
target/riscv: Fix size of badaddr and bins
target/riscv: Fix size of guest_phys_fault_addr
target/riscv: Fix size of priv_ver and vext_ver
target/riscv: Fix size of retxh
target/riscv: Fix size of ssp
target/riscv: Fix size of excp_uw2
target/riscv: Fix size of sw_check_code
target/riscv: Fix size of priv
target/riscv: Fix size of gei fields
target/riscv: Fix size of [m|s|vs]iselect fields
target/riscv: Fix arguments to board IMSIC emulation callbacks
target/riscv: Fix size of irq_overflow_left
target/riscv: Indent PMUFixedCtrState correctly
target/riscv: Replace target_ulong in riscv_cpu_get_trap_name()
target/riscv: Replace target_ulong in riscv_ctr_add_entry()
target/riscv: Fix size of trigger data
target/riscv: Fix size of mseccfg
... and remove it in the last one.
