Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/tlb-insns.c | 52 +++++++++++++++++++++++++++-----------
1 file changed, 37 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index 6c07839e3f..cbab7f81f9 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -1031,11 +1031,16 @@ static void tlbi_aa64_rvae2_write(CPUARMState *env,
* since we don't support flush-for-specific-ASID-only or
* flush-last-level-only.
*/
-
do_rvae_write(env, value, vae2_tlbmask(env),
tlb_force_broadcast(env));
+}
-
+static void tlbi_aa64_rvae2_write128(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ do_rvae_write128(env, vallo, valhi, vae2_tlbmask(env),
+ tlb_force_broadcast(env));
}
static void tlbi_aa64_rvae2is_write(CPUARMState *env,
@@ -1048,9 +1053,14 @@ static void tlbi_aa64_rvae2is_write(CPUARMState *env,
* since we don't support flush-for-specific-ASID-only,
* flush-last-level-only or inner/outer shareable specific flushes.
*/
-
do_rvae_write(env, value, vae2_tlbmask(env), true);
+}
+static void tlbi_aa64_rvae2is_write128(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ do_rvae_write128(env, vallo, valhi, vae2_tlbmask(env), true);
}
static void tlbi_aa64_rvae3_write(CPUARMState *env,
@@ -1202,13 +1212,17 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
.access = PL2_W,
- .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
- .writefn = tlbi_aa64_rvae2is_write },
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS |
+ ARM_CP_EL3_NO_EL2_UNDEF | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae2is_write,
+ .write128fn = tlbi_aa64_rvae2is_write128 },
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
.access = PL2_W,
- .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
- .writefn = tlbi_aa64_rvae2is_write },
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS |
+ ARM_CP_EL3_NO_EL2_UNDEF | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae2is_write,
+ .write128fn = tlbi_aa64_rvae2is_write128 },
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
.access = PL2_W,
@@ -1224,23 +1238,31 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
.access = PL2_W,
- .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
- .writefn = tlbi_aa64_rvae2is_write },
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS |
+ ARM_CP_EL3_NO_EL2_UNDEF | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae2is_write,
+ .write128fn = tlbi_aa64_rvae2is_write128 },
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
.access = PL2_W,
- .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
- .writefn = tlbi_aa64_rvae2is_write },
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS |
+ ARM_CP_EL3_NO_EL2_UNDEF | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae2is_write,
+ .write128fn = tlbi_aa64_rvae2is_write128 },
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
.access = PL2_W,
- .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
- .writefn = tlbi_aa64_rvae2_write },
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS |
+ ARM_CP_EL3_NO_EL2_UNDEF | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae2_write,
+ .write128fn = tlbi_aa64_rvae2_write128 },
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
.access = PL2_W,
- .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
- .writefn = tlbi_aa64_rvae2_write },
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS |
+ ARM_CP_EL3_NO_EL2_UNDEF | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae2_write,
+ .write128fn = tlbi_aa64_rvae2_write128 },
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
--
2.43.0
