> > * XSAVES feature bit (CPUID 0xD.0x1.EAX[bit 3]):
> >
> > Arch lbr state is a supervisor state, which requires the XSAVES
> > feature support. Enumerate supported supervisor state based on XSAVES
> > feature bit in x86_cpu_enable_xsave_components().
> >
> > Then it's safe to drop the check on XSAVES feature support during
> > CPUID 0XD encoding.
...
> > +++ b/target/i386/cpu.c
> > @@ -8174,16 +8174,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
> > uint32_t count,
> > *ebx = xsave_area_size(xstate, true);
> > *ecx = env->features[FEAT_XSAVE_XSS_LO];
> > *edx = env->features[FEAT_XSAVE_XSS_HI];
> > - if (kvm_enabled() && cpu->enable_pmu &&
> > - (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) &&
> > - (*eax & CPUID_XSAVE_XSAVES)) {
> > - *ecx |= XSTATE_ARCH_LBR_MASK;
> > - } else {
> > - *ecx &= ~XSTATE_ARCH_LBR_MASK;
> > - }
>
> > - } else if (count == 0xf && cpu->enable_pmu
> > - && (env->features[FEAT_7_0_EDX] &
> > CPUID_7_0_EDX_ARCH_LBR)) {
> > - x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx);
>
> This chunk needs to be a separate patch. It's a functional change.
Already mentioned this in commit message.
