On 10/17/25 1:19 AM, Nicolin Chen wrote:
> On Mon, Sep 29, 2025 at 02:36:35PM +0100, Shameer Kolothum wrote:
>> When the guest reboots with devices in nested mode (S1 + S2), any QEMU/UEFI
>> access to those devices can fail because S1 translation is not valid during
>> the reboot. For example, a passthrough NVMe device may hold GRUB boot info
>> that UEFI tries to read during the reboot.
>>
>> Set S1 to bypass mode during reset to avoid such failures.
> GBPA is set to bypass on reset so I think it's fine. Yet, maybe the
> code should check that.
shouldn't we check its actual value before setting bypass?
By the way the spec says is ABORT is set to 0x0:
"Do not abort incoming transactions. Transactions bypass the SMMU with
attributes given by other fields in this register."
Wondering about those attributes and they can apply on the host?
Eric
>
>> Reported-by: Matthew R. Ochs <[email protected]>
>> Signed-off-by: Shameer Kolothum <[email protected]>
>> ---
>> hw/arm/smmuv3-accel.c | 29 +++++++++++++++++++++++++++++
>> hw/arm/smmuv3-accel.h | 4 ++++
>> hw/arm/smmuv3.c | 1 +
>> 3 files changed, 34 insertions(+)
>>
>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
>> index defeddbd8c..8396053a6c 100644
>> --- a/hw/arm/smmuv3-accel.c
>> +++ b/hw/arm/smmuv3-accel.c
>> @@ -634,6 +634,35 @@ static const PCIIOMMUOps smmuv3_accel_ops = {
>> .get_msi_address_space = smmuv3_accel_find_msi_as,
>> };
>>
>> +/*
>> + * If the guest reboots and devices are configured for S1+S2, Stage1 must
>> + * be switched to bypass. Otherwise, QEMU/UEFI may fail when accessing a
>> + * device, e.g. when UEFI retrieves boot partition information from an
>> + * assigned vfio-pci NVMe device.
>> + */
>> +void smmuv3_accel_attach_bypass_hwpt(SMMUv3State *s)
> We could rename it to something like smmuv3_accel_reset().
>
> Nicolin
>
