On 17/10/25 10:53, Peter Maydell wrote:
In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when we added the code for setting up the registers correctly on trapping FP exceptions, we accidentally broke the handling of the flag bits for non-trapping exceptions.In update_fr0_op() we incorrectly zero out the flag bits and the C bit, so any fp operation would clear previously set flag bits. We also stopped setting the flag bits when the fp operation raises an exception and the trap is not enabled. Adjust the code so that we set the Flag bits for every exception that happened and where the trap is not enabled. (This is the correct behaviour for the case where an instruction triggers two exceptions, one of which traps and one of which does not; that can only happen for inexact + underflow or inexact + overflow.) Cc: [email protected] Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158 Signed-off-by: Peter Maydell <[email protected]> --- target/hppa/fpu_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
Queued via hw-misc, thanks!
