The following allows support for component basic back invalidation discovery and config, by exposing the BI routing table and decoder registers. Instead of going the type2[0] route, this series proposes adding support for type3 hdm-db, which allows a more direct way of supporting BI in qemu.
Changes from v3 (https://lore.kernel.org/all/[email protected]/): o Fix Flexbus caps bits in patch 1. (Jonathan) o Flipped the bi arg to true for hard-configured components in patch 4 (Jonathan). o Expose the BI routing table only if the sw upstream port is in Flit mode. o Removed the mem-path= arg in the documentation as it deals with volatile (Donjoo). Changes from v2 (https://lore.kernel.org/linux-cxl/[email protected]/): o Renamed 256b-flit to x-256b-flit (mst) o Added a brief description of flit mode in patch 1 changelog (Markus) o Added missing hdm-db parameter which went missing in v2. o Replaced the new CXL3_TYPE3_DEVICE with passing 'bi' params. (Jonathan) o Fixed writemask bits in patch 4. (Jonathan) o Misc cleanups in patch 4. (Jonathan) o New patch 5 to remove register special_ops read() cb. (Jonathan) Changes from v1 (https://lore.kernel.org/qemu-devel/[email protected]/): o Further lnk training in patch 1. (Jonathan) o Flit parameter changed to bool in patch 1. (Jonathan) o Do not set 68B in component Flexbus Port when in flitmode in patch 1. o Doc build fixlet in patch 3. o Pass the exact type3 type in cxl_component_create_dvsec() - unused, but better for keeping track, in patch 4. o Change doc example to volatile device in patch 4. Changes from rfc (https://lore.kernel.org/qemu-devel/[email protected]/): o Added 256b-flit parameter, per Jonathan. o Added window restrictions changes. o Dropped rfc tag. Patch 1 introduces the flit mode parameter. Patch 2 is lifted from Ira's series with some small (but non-trivial) changes. Patch 3 updates the cfmw restrictions option. Patch 4 adds BI decoder/rt register support to enable type3 HDM-DB. Patch 5 is a small cleanup. Testing wise, this has passed relevant kernel side BI register IO flows for BI-ID setup and deallocation. The next step for this would be to add UIO support to qemu. Applies against branch 'origin/cxl-2025-10-03-draft' from Jonathan's repository. Thanks! Davidlohr Bueso (4): hw/pcie: Support enabling flit mode hw/cxl: Allow BI by default in Window restrictions hw/cxl: Support type3 HDM-DB hw/cxl: Remove register special_ops->read() Ira Weiny (1): hw/cxl: Refactor component register initialization docs/system/devices/cxl.rst | 23 +++ hw/cxl/cxl-component-utils.c | 211 ++++++++++++++++------ hw/cxl/cxl-host.c | 2 +- hw/mem/cxl_type3.c | 15 +- hw/pci-bridge/cxl_downstream.c | 10 +- hw/pci-bridge/cxl_root_port.c | 11 +- hw/pci-bridge/cxl_upstream.c | 18 +- hw/pci-bridge/gen_pcie_root_port.c | 1 + hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci/pcie.c | 23 ++- include/hw/cxl/cxl_component.h | 87 +++++++-- include/hw/cxl/cxl_device.h | 4 + include/hw/pci-bridge/cxl_upstream_port.h | 1 + include/hw/pci/pcie.h | 2 +- include/hw/pci/pcie_port.h | 1 + qapi/machine.json | 3 +- qemu-options.hx | 4 +- 17 files changed, 319 insertions(+), 99 deletions(-) -- 2.39.5
