On Tue, Nov 11, 2025 at 03:29:44PM -0300, Daniel Henrique Barboza wrote: > Add documentation on the new experimental board rvsp-ref. > > Signed-off-by: Daniel Henrique Barboza <[email protected]> > --- > docs/system/riscv/rvsp-ref.rst | 28 ++++++++++++++++++++++++++++ > docs/system/target-riscv.rst | 1 + > 2 files changed, 29 insertions(+) > create mode 100644 docs/system/riscv/rvsp-ref.rst > > diff --git a/docs/system/riscv/rvsp-ref.rst b/docs/system/riscv/rvsp-ref.rst > new file mode 100644 > index 0000000000..3889fce413 > --- /dev/null > +++ b/docs/system/riscv/rvsp-ref.rst > @@ -0,0 +1,28 @@ > +Experimental RISC-V Server Platform Reference board (``rvsp-ref``) > +================================================================== > + > +The RISC-V Server Platform specification `spec`_ defines a standardized > +set of hardware and software capabilities that portable system software, > +such as OS and hypervisors, can rely on being present in a RISC-V server > +platform. This machine aims to emulate this specification, providing > +an environment for firmware/OS development and testing. > + > +The main features included in rvsp-ref are: > + > +* a new CPU type rvsp-ref CPU for server platform compliance > +* AIA > +* PCIe AHCI > +* PCIe NIC > +* No virtio mmio bus > +* No fw_cfg device > +* No ACPI table > +* Minimal device tree nodes > + > +The board is being provisioned as *experimental* because QEMU isn't > +100% compliant with the specification at this moment - we do not have > +support for the mandatory 'sdext' extension. The existence of the board > +is beneficial to the development of the ecossystem around the specification, > +so we're choosing the make the board available even in an incomplete state. > +When 'sdext' is implemented we'll remove the 'experimental' tag from it.
'experimental' needs to stay until the 1.0 spec is ratified. Or, see my comments in a previous patch about versioning the board instead. Thanks, drew > + > +.. _spec: https://github.com/riscv-non-isa/riscv-server-platform > diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst > index 89b2cb732c..2ed337c8cf 100644 > --- a/docs/system/target-riscv.rst > +++ b/docs/system/target-riscv.rst > @@ -72,6 +72,7 @@ undocumented; you can get a complete list by running > riscv/sifive_u > riscv/virt > riscv/xiangshan-kunminghu > + riscv/rvsp-ref > > RISC-V CPU firmware > ------------------- > -- > 2.51.1 > >
