On Mon, Nov 3, 2025 at 1:37 PM <[email protected]> wrote: > > From: Alistair Francis <[email protected]> > > This is the first 8 patches (one of which has been removed) from Anton's > series [1], plus an extra cleanup patch at the end. > > This addresses the comments I had about Anton's changes to > riscv_pmu_ctr_get_fixed_counters_val(). > > Besides my new patch and removing a patch the actual changes are > limited, so I have kept all of the Reviewed-by tags. > > 1: https://patchew.org/QEMU/[email protected]/ > > Alistair Francis (1): > target/riscv: Remove upper_half from > riscv_pmu_ctr_get_fixed_counters_val > > Anton Johansson (7): > target/riscv: Fix size of trivial CPUArchState fields > target/riscv: Fix size of mhartid > target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read > target/riscv: Combine mhpmevent and mhpmeventh > target/riscv: Combine mcyclecfg and mcyclecfgh > target/riscv: Combine minstretcfg and minstretcfgh > target/riscv: Combine mhpmcounter and mhpmcounterh
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.h | 106 +++++++++--------- > target/riscv/cpu_helper.c | 2 +- > target/riscv/csr.c | 221 ++++++++++++++++--------------------- > target/riscv/machine.c | 99 ++++++++--------- > target/riscv/pmu.c | 150 ++++++------------------- > target/riscv/tcg/tcg-cpu.c | 2 +- > 6 files changed, 227 insertions(+), 353 deletions(-) > > -- > 2.51.1 >
