If the guest misprograms the PLL registers to request a zero divisor, we currently fall over with a division by zero:
../../hw/misc/npcm_clk.c:221:14: runtime error: division by zero SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../../hw/misc/npcm_clk.c:221:14 Thread 1 "qemu-system-aar" received signal SIGFPE, Arithmetic exception. 0x00005555584d8f6d in npcm7xx_clk_update_pll (opaque=0x7fffed159a20) at ../../hw/misc/npcm_clk.c:221 221 freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); Avoid this by treating this invalid setting like a stopped clock (setting freq to 0). Cc: [email protected] Resolves: https://gitlab.com/qemu-project/qemu/-/issues/549 Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Message-id: [email protected] --- hw/misc/npcm_clk.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index c48d40b4468..e202a8a2998 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -212,13 +212,14 @@ static void npcm7xx_clk_update_pll(void *opaque) { NPCM7xxClockPLLState *s = opaque; uint32_t con = s->clk->regs[s->reg]; - uint64_t freq; + uint64_t freq, freq_div; /* The PLL is grounded if it is not locked yet. */ if (con & PLLCON_LOKI) { freq = clock_get_hz(s->clock_in); freq *= PLLCON_FBDV(con); - freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); + freq_div = PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); + freq = freq_div ? freq / freq_div : 0; } else { freq = 0; } -- 2.43.0
