On 11/17/25 02:40, Gabriel Brookman wrote:
Previously, the bits used to advertise the various MTE4 features were
not explicitly set for -cpu max. This commit calls out these bits and
explicitly unsets them. At the end of the patch series, a second commit
will explicitly set all of them.
Signed-off-by: Gabriel Brookman <[email protected]>
---
target/arm/tcg/cpu64.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 6871956382..ca9557f4cf 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1281,8 +1281,16 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
t = FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */
+ t = FIELD_DP64(t, ID_AA64PFR1,
+ MTEX, 0); /* FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS
*/
SET_IDREG(isar, ID_AA64PFR1, t);
+ t = GET_IDREG(isar, ID_AA64PFR2);
+ t = FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 0); /* FEAT_MTE_TAGGED_FAR */
+ t = FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 0); /* FEAT_MTE_STORE_ONLY
*/
+ t = FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 0); /* FEAT_MTE_PERM */
+ SET_IDREG(isar, ID_AA64PFR2, t);
+
t = GET_IDREG(isar, ID_AA64MMFR0);
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
They weren't explicitly set, but the whole ARMCPU structure, including the isar field, was
zeroed upon object creation. So I don't really see the point in this patch.
r~
