On Tue, Nov 18, 2025 at 7:43 AM Zhao Liu <[email protected]> wrote:
>
> From: Zide Chen <[email protected]>
>
> Cache EGPR[16] in CPUX86State to store APX's EGPR value.
Please change regs[] to have 32 elements instead; see the attached
patch for a minimal starting point. You can use VMSTATE_SUB_ARRAY to
split their migration data in two parts. You'll have to create a
VMSTATE_UINTTL_SUB_ARRAY similar to VMSTATE_UINT64_SUB_ARRAY.
To support HMP you need to adjust target/i386/monitor.c and
target/i386/cpu-dump.c. Please make x86_cpu_dump_state print R16...R31
only if APX is enabled in CPUID.
Also, it would be best for the series to include gdb support. APX is
supported by gdb as a "coprocessor", the easiest way to do it is to
copy what riscv_cpu_register_gdb_regs_for_features() does for the FPU,
and copy
https://github.com/intel/gdb/blob/master/gdb/features/i386/64bit-apx.xml
into QEMU's gdb-xml/ directory.
Paolo
> Tested-by: Xudong Hao <[email protected]>
> Signed-off-by: Zide Chen <[email protected]>
> Co-developed-by: Zhao Liu <[email protected]>
> Signed-off-by: Zhao Liu <[email protected]>
> ---
> target/i386/cpu.h | 1 +
> target/i386/xsave_helper.c | 14 ++++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index bc7e16d6e6c1..48d4d7fcbb9c 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1969,6 +1969,7 @@ typedef struct CPUArchState {
> #ifdef TARGET_X86_64
> uint8_t xtilecfg[64];
> uint8_t xtiledata[8192];
> + uint64_t egprs[EGPR_NUM];
> #endif
>
> /* sysenter registers */
> diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c
> index 996e9f3bfef5..2e9265045520 100644
> --- a/target/i386/xsave_helper.c
> +++ b/target/i386/xsave_helper.c
> @@ -140,6 +140,13 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf,
> uint32_t buflen)
>
> memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata));
> }
> +
> + e = &x86_ext_save_areas[XSTATE_APX_BIT];
> + if (e->size && e->offset && buflen) {
> + XSaveAPX *apx = buf + e->offset;
> +
> + memcpy(apx, &env->egprs, sizeof(env->egprs));
> + }
> #endif
> }
>
> @@ -275,5 +282,12 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void
> *buf, uint32_t buflen)
>
> memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata));
> }
> +
> + e = &x86_ext_save_areas[XSTATE_APX_BIT];
> + if (e->size && e->offset) {
> + const XSaveAPX *apx = buf + e->offset;
> +
> + memcpy(&env->egprs, apx, sizeof(env->egprs));
> + }
> #endif
> }
> --
> 2.34.1
>
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index cee1f692a1c..0816f1dd22f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1638,12 +1638,15 @@ typedef struct {
uint64_t mask;
} MTRRVar;
+#define CPU_NB_EREGS64 32
#define CPU_NB_REGS64 16
#define CPU_NB_REGS32 8
#ifdef TARGET_X86_64
+#define CPU_NB_EREGS CPU_NB_EREGS64
#define CPU_NB_REGS CPU_NB_REGS64
#else
+#define CPU_NB_EREGS CPU_NB_REGS32
#define CPU_NB_REGS CPU_NB_REGS32
#endif
@@ -1845,7 +1848,7 @@ typedef struct CPUCaches {
typedef struct CPUArchState {
/* standard registers */
- target_ulong regs[CPU_NB_REGS];
+ target_ulong regs[CPU_NB_EREGS];
target_ulong eip;
target_ulong eflags; /* eflags register. During CPU emulation, CC
flags and DF are set to zero because they are
@@ -1902,7 +1905,7 @@ typedef struct CPUArchState {
float_status mmx_status; /* for 3DNow! float ops */
float_status sse_status;
uint32_t mxcsr;
- ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
+ ZMMReg xmm_regs[CPU_NB_EREGS] QEMU_ALIGNED(16);
ZMMReg xmm_t0 QEMU_ALIGNED(16);
MMXReg mmx_t0;
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 04c49e802d7..17d8e350834 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -125,6 +125,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
as if we're on a 64-bit cpu. */
+ // TODO: APX registers
if (n < CPU_NB_REGS) {
if (TARGET_LONG_BITS == 64) {
if (env->hflags & HF_CS64_MASK) {
