Hello, On Wed, 10 Dec 2025, Chad Jablonski wrote:
Hey BALATON, just a friendly ping on the v3 HOST_DATA series. If there's something I can take a look at as far as hardware validation or anything else let me know! In the meantime I've been getting familiar with CCE and poking at the microcode a bit.
I haven't missed it but I did not have time to test and review it yet. I hoped somebody else could also help out but I still intend to review it when I have more time. For the CCE I've restored the ticket I got about it before here: https://codeberg.org/qmiga/pages/issues/3 which has the info I've collected so far that may help but I could not find info on the microcode of these older ATI cards, Only newer versions seem to be known that are linked in the ticket. So unless you can find out how it works the way to go may be to parse the packets directly the same way as Xenia emulator does and not trying to run the microcode but it would be nice to emulate the micro engine if the microcode can be reversed or understood enough. Newer versions of the microcode appear to have short segments for each packet type that do simple operations, mainly stuffing data in the command FIFO so that FIFO may also need to be implemented first then another possible improvement is to run the drawing engine in a separate thread asynchronously fed through the command FIFO as it works on the real chip.
Regards, BALATON Zoltan
