> -----Original Message----- > From: Yubin Zou <[email protected]> > Sent: Wednesday, December 17, 2025 8:22 AM > To: [email protected] > Cc: Cédric Le Goater <[email protected]>; Peter Maydell > <[email protected]>; Steven Lee <[email protected]>; Troy > Lee <[email protected]>; Jamin Lin <[email protected]>; Andrew > Jeffery <[email protected]>; Joel Stanley <[email protected]>; > Fabiano Rosas <[email protected]>; Laurent Vivier <[email protected]>; > Paolo Bonzini <[email protected]>; Kane Chen > <[email protected]>; Nabih Estefan <[email protected]>; > [email protected]; Yubin Zou <[email protected]> > Subject: [PATCH v4 2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors > for SGPIO pins > > The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are > implemented to get and set the level of individual SGPIO pins. These are then > exposed as boolean properties on the SGPIO device object. > > Signed-off-by: Yubin Zou <[email protected]> > --- > hw/gpio/aspeed_sgpio.c | 77 > ++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > > diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index > 3fc750fe619dcb6f9a1f2486999e945002a6df13..dc2df137db247c178adc05807 > bd0595fc0cb5c52 100644 > --- a/hw/gpio/aspeed_sgpio.c > +++ b/hw/gpio/aspeed_sgpio.c > @@ -84,6 +84,73 @@ static void aspeed_sgpio_2700_write(void *opaque, > hwaddr offset, uint64_t data, > } > } > > +static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin) { > + uint32_t value = s->ctrl_regs[pin >> 1]; > + bool is_input = !(pin % 2); > + uint32_t bit_mask = 0; > + > + if (is_input) { > + bit_mask = SGPIO_SERIAL_IN_VAL_MASK; > + } else { > + bit_mask = SGPIO_SERIAL_OUT_VAL_MASK; > + } > + > + return value & bit_mask; > +} > + > +static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, > +bool level) { > + uint32_t value = s->ctrl_regs[pin >> 1]; > + bool is_input = !(pin % 2); > + uint32_t bit_mask = 0; > + > + if (is_input) { > + bit_mask = SGPIO_SERIAL_IN_VAL_MASK; > + } else { > + bit_mask = SGPIO_SERIAL_OUT_VAL_MASK; > + } > + > + if (level) { > + value |= bit_mask; > + } else { > + value &= ~bit_mask; > + } > + s->ctrl_regs[pin >> 1] = value; > +} > + > +static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) { > + bool level = true; > + int pin = 0xfff; > + AspeedSGPIOState *s = ASPEED_SGPIO(obj); > + > + if (sscanf(name, "sgpio%03d", &pin) != 1) { > + error_setg(errp, "%s: error reading %s", __func__, name); > + return; > + } > + level = aspeed_sgpio_get_pin_level(s, pin); > + visit_type_bool(v, name, &level, errp); } > + > +static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) { > + bool level; > + int pin = 0xfff; > + AspeedSGPIOState *s = ASPEED_SGPIO(obj); > + > + if (!visit_type_bool(v, name, &level, errp)) { > + return; > + } > + if (sscanf(name, "sgpio%03d", &pin) != 1) { > + error_setg(errp, "%s: error reading %s", __func__, name); > + return; > + } > + aspeed_sgpio_set_pin_level(s, pin, level); } > + > static const MemoryRegionOps aspeed_gpio_2700_ops = { > .read = aspeed_sgpio_2700_read, > .write = aspeed_sgpio_2700_write, > @@ -107,6 +174,15 @@ static void aspeed_sgpio_realize(DeviceState *dev, > Error **errp) > sysbus_init_mmio(sbd, &s->iomem); > } > > +static void aspeed_sgpio_init(Object *obj) { > + for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) { > + g_autofree char *name = g_strdup_printf("sgpio%03d", i); > + object_property_add(obj, name, "bool", aspeed_sgpio_get_pin, > + aspeed_sgpio_set_pin, NULL, NULL); > + } > +} > + > static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) { > DeviceClass *dc = DEVICE_CLASS(klass); @@ -136,6 +212,7 @@ static > const TypeInfo aspeed_sgpio_ast2700_info = { > .name = TYPE_ASPEED_SGPIO "-ast2700", > .parent = TYPE_ASPEED_SGPIO, > .class_init = aspeed_sgpio_2700_class_init, > + .instance_init = aspeed_sgpio_init, > }; > > static void aspeed_sgpio_register_types(void) > > -- > 2.52.0.305.g3fc767764a-goog
Reviewed-by: Kane Chen <[email protected]> Best Regards, Kane
