On 2025/12/21 下午8:22, Yao Zi wrote:
IOCSRs could be accessed in any sizes from 1 to 8 bytes as long as the
address is aligned, regardless whether through MMIO or iocsr{rd,wr}
instructions. Lower min_access_size to 1 byte for IOCSR memory region to
match real-hardware behavior.
Hi Yao,
What is the detailed problem you encountered? Or just look through code
and think that it should be so.
IOCSR supports 1/2/4/8 byte access like MMIO, however here is IOCSR MISC
device rather than IOCSR bus emulation. What is the usage and scenery to
read IOCSR MISC device with one byte?
It is similar with other device emulation with MMIO, such as e1000e with
4 bytes aligned rather than any byte:
static const MemoryRegionOps mmio_ops = {
.read = e1000e_mmio_read,
.write = e1000e_mmio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
};
Regards
Bibo Mao
Fixes: f84a2aacf5d1 ("target/loongarch: Add LoongArch IOCSR instruction")
Signed-off-by: Yao Zi <[email protected]>
---
hw/loongarch/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 49434ad1828b..5cc57e9b5aa7 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -692,7 +692,7 @@ static const MemoryRegionOps virt_iocsr_misc_ops = {
.write_with_attrs = virt_iocsr_misc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
- .min_access_size = 4,
+ .min_access_size = 1,
.max_access_size = 8,
},
.impl = {
