---
include/hw/arm/aspeed_soc.h | 3 +-
include/hw/misc/aspeed_pwm.h | 31 +++++++++
hw/misc/aspeed_pwm.c | 121
+++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 4 ++
5 files changed, 159 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/aspeed_pwm.h
create mode 100644 hw/misc/aspeed_pwm.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index bca10c387b..5b0680f319 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -28,6 +28,7 @@
#include "hw/misc/aspeed_hace.h"
#include "hw/misc/aspeed_sbc.h"
#include "hw/misc/aspeed_sli.h"
+#include "hw/misc/aspeed_pwm.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
@@ -108,7 +109,7 @@ struct AspeedSoCState {
UnimplementedDeviceState video;
UnimplementedDeviceState emmc_boot_controller;
UnimplementedDeviceState dpmcu;
- UnimplementedDeviceState pwm;
+ AspeedPWMState pwm;
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
UnimplementedDeviceState ltpi;
diff --git a/include/hw/misc/aspeed_pwm.h
b/include/hw/misc/aspeed_pwm.h new file mode 100644 index
0000000000..13dc3ea45b
--- /dev/null
+++ b/include/hw/misc/aspeed_pwm.h
@@ -0,0 +1,31 @@
+/*
+ * ASPEED PWM Controller
+ *
+ * Copyright (C) 2017-2021 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef ASPEED_PWM_H
+#define ASPEED_PWM_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_PWM "aspeed.pwm"
+#define ASPEED_PWM(obj) OBJECT_CHECK(AspeedPWMState, (obj),
+TYPE_ASPEED_PWM)
+
+#define ASPEED_PWM_NR_REGS (0x10C >> 2)
+
+typedef struct AspeedPWMState {
+ /* <private> */
+ SysBusDevice parent;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ uint32_t regs[ASPEED_PWM_NR_REGS]; } AspeedPWMState;
+
+#endif /* _ASPEED_PWM_H_ */
diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c new file
mode
100644 index 0000000000..de209274af
--- /dev/null
+++ b/hw/misc/aspeed_pwm.c
@@ -0,0 +1,121 @@
+/*
+ * ASPEED PWM Controller
+ *
+ * Copyright (C) 2017-2021 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/misc/aspeed_pwm.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+
+#include "trace.h"
+
+static uint64_t aspeed_pwm_read(void *opaque, hwaddr addr,
+ unsigned int size) {
+ AspeedPWMState *s = ASPEED_PWM(opaque);
+ uint64_t val = 0;
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_PWM_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%"
HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ } else {
+ val = s->regs[addr];
+ }
+
+ trace_aspeed_pwm_read(addr << 2, val);
+
+ return val;
+}
+
+static void aspeed_pwm_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size) {
+ AspeedPWMState *s = ASPEED_PWM(opaque);
+
+ trace_aspeed_pwm_write(addr, data);
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_PWM_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%"
HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ return;
+ }
+
+ s->regs[addr] = data;
+}
+
+static const MemoryRegionOps aspeed_pwm_ops = {
+ .read = aspeed_pwm_read,
+ .write = aspeed_pwm_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_pwm_reset(DeviceState *dev) {
+ struct AspeedPWMState *s = ASPEED_PWM(dev);
+
+ memset(s->regs, 0, sizeof(s->regs)); }
+
+static void aspeed_pwm_realize(DeviceState *dev, Error **errp) {
+ AspeedPWMState *s = ASPEED_PWM(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_pwm_ops, s,
+ TYPE_ASPEED_PWM, 0x1000);
+
+ sysbus_init_mmio(sbd, &s->iomem); }
+
+static const VMStateDescription vmstate_aspeed_pwm = {
+ .name = TYPE_ASPEED_PWM,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedPWMState,
ASPEED_PWM_NR_REGS),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void aspeed_pwm_class_init(ObjectClass *klass, const void
+*data) {
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_pwm_realize;
+ device_class_set_legacy_reset(dc, aspeed_pwm_reset);
+ dc->desc = "Aspeed PWM Controller";
+ dc->vmsd = &vmstate_aspeed_pwm;
+}
+
+static const TypeInfo aspeed_pwm_info = {
+ .name = TYPE_ASPEED_PWM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedPWMState),
+ .class_init = aspeed_pwm_class_init, };
+
+static void aspeed_pwm_register_types(void) {
+ type_register_static(&aspeed_pwm_info);
+}
+
+type_init(aspeed_pwm_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build index
45b16e7797..7afe1d0009 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -137,6 +137,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC',
if_true: files(
'aspeed_i3c.c',
'aspeed_lpc.c',
'aspeed_ltpi.c',
+ 'aspeed_pwm.c',
'aspeed_scu.c',
'aspeed_sbc.c',
'aspeed_sdmc.c',
diff --git a/hw/misc/trace-events b/hw/misc/trace-events index
eeb9243898..f7870babba 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -299,6 +299,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data)
"I3C write: offset 0x%" PRIx64
aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data)
"I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t
data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
+# aspeed_pwm.c
+aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%"
+PRIx64 " data 0x%" PRIx64 aspeed_pwm_write(uint64_t offset, uint64_t
+data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64
+
# aspeed_sdmc.c
aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 "
data: 0x%" PRIx64
aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 "
data: 0x%" PRIx64
