The Open Multi-Processor Interrupt Controller (ompic) is only used by the OpenRISC target, which is only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly using DEVICE_BIG_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- hw/intc/ompic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c index 047c367478d..ee34501f675 100644 --- a/hw/intc/ompic.c +++ b/hw/intc/ompic.c @@ -96,7 +96,7 @@ static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) static const MemoryRegionOps ompic_ops = { .read = ompic_read, .write = ompic_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_BIG_ENDIAN, .impl = { .max_access_size = 8, }, -- 2.52.0
