Hi,
In this version I addressed Konstantin review comments from v2. They
consisted on fixes in TE_CONTROL and TR_RAM_CONTROL fields from the
trace encoder and trace ram sink and changes in in the e-trace message
helpers.
And in case someone notices: an administrative change was made w.r.t the
authors email addresses and all copyright for new files: Qualcomm bought
Ventana MicroSystems and it's now sponsoring this new version and all
future versions of this work.
Despite the big changelog no functional change was made in comparison
with v2.
Patches based on alistair/riscv-to-apply.next.
Changes from v2:
- patch 1:
- changed RSVP5 TE_CONTROL field size from 4 to 5
- patch 2:
- changed RSVP2 TR_RAM_CONTROL field size from 2 to 3
- changed RSVP4 TR_RAM_CONTROL field size from 16 to 17
- patch 6:
- add an enum to store payload size macros
- rv_etrace_write_bits() returns the number of written bits
- use "/" and "%" instead of bit shift operations in
rv_etrace_write_bits
- use MIN() to calculate 'byte_bits' in rv_etrace_write_bits
- use deposit32() to write bytes[byte_index]
- rv_etrace_write_header() now returns the number of written bits
- write 'flow' and 'extend' in write_header()
- assign 'addressLow' and 'addressHigh' in 'payload' declaration
- patch 10:
- add TRAP_PAYLOAD_SIZE_64BITS to RVTraceMessagePayloadSize enum;
- assign 'addressLow' and 'addressHigh' in 'payload' declaration
- use the return of write_header() and write_bits() to increment bit_pos
- patch 13:
- add FORMAT2_PAYLOAD_SIZE_64BITS to RVTraceMessagePayloadSize enum;
- assign 'addressLow' and 'addressHigh' in 'payload' declaration
- use the return of write_header() and write_bits() to increment bit_pos
- patch 15:
- add FORMAT1_BASE_PAYLOAD_SIZE_64BITS and FORMAT1_PAYLOAD_MIN_SIZE_64BITS
to RVTraceMessagePayloadSize enum;
- assign 'addressLow' and 'addressHigh' in 'payload' declaration
- use the return of write_header() and write_bits() to increment bit_pos
- v2 link:
https://lore.kernel.org/qemu-riscv/[email protected]/
Daniel Henrique Barboza (16):
hw/riscv: Trace Encoder initial impl
hw/riscv: Trace RAM Sink initial impl
hw/riscv/trace-encoder: add trace start/stop logic
hw/riscv/virt.c: add trace encoders and trace ram sinks
hw/riscv: add e-trace message helpers
target/riscv: add initial trace instrumentation
hw/riscv/trace-encoder: write e-trace packets to RAM sink
test/qtest: add riscv-trace-test.c
hw/riscv/rv-trace-messages.c: add encoded trap message
hw/riscv, target/riscv: send trace trap messages
target/riscv, hw/riscv: send trace ppccd packets
hw/riscv/trace: add format2 msg helper
hw/riscv, target/riscv: send resync updiscon trace packets
hw/riscv/rv-trace-messages: add format 1 msgs with branch info
hw/riscv/trace-encoder: send branches info
hw/riscv/trace: update branch bit in sync messages
Mayuresh Chitale (1):
hw/riscv/virt.c add trace encoder and ramsink fdt nodes
hw/riscv/Kconfig | 5 +
hw/riscv/meson.build | 2 +
hw/riscv/rv-trace-messages.c | 340 ++++++++++
hw/riscv/rv-trace-messages.h | 40 ++
hw/riscv/trace-encoder.c | 609 ++++++++++++++++++
hw/riscv/trace-encoder.h | 62 ++
hw/riscv/trace-events | 9 +
hw/riscv/trace-ram-sink.c | 263 ++++++++
hw/riscv/trace-ram-sink.h | 83 +++
hw/riscv/virt.c | 135 ++++
include/hw/riscv/virt.h | 2 +
target/riscv/cpu.h | 11 +
target/riscv/cpu_helper.c | 26 +-
target/riscv/helper.h | 6 +
.../riscv/insn_trans/trans_privileged.c.inc | 11 +
target/riscv/insn_trans/trans_rvi.c.inc | 15 +
target/riscv/meson.build | 3 +-
target/riscv/tcg/tcg-cpu.c | 5 +
target/riscv/trace_helper.c | 62 ++
target/riscv/translate.c | 19 +
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-trace-test.c | 120 ++++
22 files changed, 1827 insertions(+), 3 deletions(-)
create mode 100644 hw/riscv/rv-trace-messages.c
create mode 100644 hw/riscv/rv-trace-messages.h
create mode 100644 hw/riscv/trace-encoder.c
create mode 100644 hw/riscv/trace-encoder.h
create mode 100644 hw/riscv/trace-ram-sink.c
create mode 100644 hw/riscv/trace-ram-sink.h
create mode 100644 target/riscv/trace_helper.c
create mode 100644 tests/qtest/riscv-trace-test.c
--
2.51.1
