On 11 June 2012 16:03, Anthony Liguori <anth...@codemonkey.ws> wrote: > On 06/11/2012 09:53 AM, Peter Maydell wrote: >> In hardware (at least for AXI) they're the same thing. A DMA >> controller is a bus master, just like a CPU. They don't care >> whether the slave is RAM or a device, they're just issuing >> memory transactions to addresses. > > It looks like the AXI stream interface also includes a word array. I can't > tell though whether this is just a decomposed scatter/gather list though. > > There doesn't appear to be a notion of an address though. You could make > all operations go to address 0 though but it makes me wonder if that's > stretching the concept of DMA a bit too much.
Yeah, I've probably been confusing things a little there, sorry. AXI-Stream is an addressless data stream (not necessarily point-to-point, the protocol includes TDEST signals to indicate the 'destination' for a data stream, so you could have a multiple-master-multiple-slave config, or a config with a slave that accepted several incoming streams over the same interface). AXI is the general address-based interface. (Have just read the spec, and AXI-Stream has a number of interesting features including optional end-of-packet signals, and the ability to say "these bytes in the data stream are to be ignored" so you can have a transfer which updates eg bytes 1-5 and 8-15 at the destination but leaves 6-7 untouched.) -- PMM