There is no equivalent access_aa32_tid5() (HCR_EL2.TID5 only exists starting from v8); rename access_aa64_tid5() to access_tid5() to line up with the naming we now have for the TID1 and TID3 check functions.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0896e90965..b914988ac9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5425,8 +5425,8 @@ static const ARMCPRegInfo dcpodp_reg[] = { .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, }; -static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult access_tid5(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) { if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { return CP_ACCESS_TRAP_EL2; @@ -7449,7 +7449,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo gmid_reginfo = { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, - .access = PL1_R, .accessfn = access_aa64_tid5, + .access = PL1_R, .accessfn = access_tid5, .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, }; define_one_arm_cp_reg(cpu, &gmid_reginfo); -- 2.47.3
