On Wed, 31 Dec 2025, Chad Jablonski wrote:
The PM4_BUFFER_CNTL register is used to set up the CCE FIFO. These are straightforward reads and writes. Future CCE patches make use of this state.
This register does not seem to be documented in Rage 128 Pro register reference and the ATI M6/RV100 seems to have different bits. Since the CCE is mostly used by Radeon drivers and there seem to be differences I wonder if it's worth implementing CCE for Rage 128 when it's not the same as the Radeon one and should we insted target Radeon CCE instead? I only know about the MacOS driver that uses CCE with Rage128 (maybe some Windows and more advanced Linux drivers exist) but all almost all Radeon drivers use CCE so that seems more important to me. What do you think? Did you consider the differences between Radeon CCE?
Regards, BALATON Zoltan
Signed-off-by: Chad Jablonski <[email protected]> --- hw/display/ati.c | 11 +++++++++++ hw/display/ati_cce.h | 4 ++++ hw/display/ati_regs.h | 12 ++++++++++++ 3 files changed, 27 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index e291926470..a4bef92efd 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -535,6 +535,11 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) */ s->cce.microcode.raddr = s->cce.microcode.addr; break; + case PM4_BUFFER_CNTL: + val = ((s->cce.buffer_mode & 0xf) << 28) | + (s->cce.no_update << 27) | + (s->cce.buffer_size_l2qw & 0x7ffffff); + break; default: break; } @@ -979,6 +984,12 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, s->cce.microcode.addr += 1; break; } + case PM4_BUFFER_CNTL: { + s->cce.buffer_size_l2qw = data & 0x7ffffff; + s->cce.no_update = (data >> 27) & 1; + s->cce.buffer_mode = (data >> 28) & 0xf; + break; + } default: break; } diff --git a/hw/display/ati_cce.h b/hw/display/ati_cce.h index f2ef1345de..25a2430c60 100644 --- a/hw/display/ati_cce.h +++ b/hw/display/ati_cce.h @@ -21,6 +21,10 @@ typedef struct ATIPM4MicrocodeState { typedef struct ATICCEState { ATIPM4MicrocodeState microcode; + /* BufferCntl */ + uint32_t buffer_size_l2qw; + bool no_update; + uint8_t buffer_mode; } ATICCEState; #endif /* ATI_CCE_H */ diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index d7127748ff..4d1ccc1434 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -378,7 +378,19 @@ #define PC_BUSY 0x80000000 #define BUS_MASTER_DIS 0x00000040 + + +/* PM4_BUFFER_CNTL buffer mode bit constants */ #define PM4_BUFFER_CNTL_NONPM4 0x00000000 +#define PM4_BUFFER_CNTL_192PIO 0x00000001 +#define PM4_BUFFER_CNTL_192BM 0x00000002 +#define PM4_BUFFER_CNTL_128PIO_64INDBM 0x00000003 +#define PM4_BUFFER_CNTL_128BM_64INDBM 0x00000004 +#define PM4_BUFFER_CNTL_64PIO_128INDBM 0x00000005 +#define PM4_BUFFER_CNTL_64BM_128INDBM 0x00000006 +#define PM4_BUFFER_CNTL_64PIO_64VCBM_64INDBM 0x00000007 +#define PM4_BUFFER_CNTL_64BM_64VCBM_64INDBM 0x00000008 +#define PM4_BUFFER_CNTL_64PIO_64VCPIO_64INPIO 0x0000000f /* DP_DATATYPE bit constants */ #define DST_8BPP 0x00000002
