On 1/1/26 12:45 AM, Aditya Gupta wrote:
> On 24/12/25 19:52, Caleb Schlossin wrote:
>
>> The Power Hypervisor for P10 expects to be able to access certain
>> Open CAPI Memory Buffer (OCMB) chip registers. Since QEMU does not
>> currently support these registers, several access errors are being
>> posted. The hypervisor is able to progress despite these errors,
>> but it does create unwanted noise on the console. Adding some
>> dummy MMIO support for this IO region in order to suppress the
>> error messages.
>
> Hi Caleb,
>
> If there any public document/spec available that documents these registers ?
> Can you please point me to it.
>
> I don't find any 'ocmb' mention in any docs here:
> https://computeexpresslink.org/resource/opencapi-specification-archive/
>
> Since a new TODO is getting introduced here to implement those register
> accesses, it can only be done if some public information is available.
>
>
> Thanks,
> - Aditya G
Aditya,
I did some searching and couldn't seem to find the registers used in any of the
public OpenCAPI documentation. I think the registers being accessed are
Vendor-specific and likely not publicly defined. If that is a new requirement,
we don't have to proceed with upstreaming of this patch and can keep it private.
Thanks,
Caleb
>
>
>> Signed-off-by: Glenn Miles <[email protected]>
>> Signed-off-by: Caleb Schlossin <[email protected]>
>> ---
>> hw/ppc/meson.build | 1 +
>> hw/ppc/pnv.c | 10 ++++
>> hw/ppc/pnv_ocmb.c | 103 ++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/pnv.h | 3 ++
>> include/hw/ppc/pnv_chip.h | 2 +
>> include/hw/ppc/pnv_ocmb.h | 38 ++++++++++++++
>> 6 files changed, 157 insertions(+)
>> create mode 100644 hw/ppc/pnv_ocmb.c
>> create mode 100644 include/hw/ppc/pnv_ocmb.h
>>
