Motivation
==========
Here is the motivation for this patch set. Please try to answer the
following 3 questions without checking QEMU source code:
1. How do you run RISC-V QEMU with a specific extension configuration?
Please try to configure an rv64im user mode QEMU before you answer
this question.
2. How do you know which extensions are supported in RISC-V QEMU?
3. How do you know which extensions are enabled in the current RISC-V QEMU?
And here are my answers to those 3 questions:
1. It's hard to configure RISC-V QEMU with a specific extension. The
correct way to configure rv64im is:
qemu-riscv64 -cpu rv64,a=false,d=false,f=false,zfa=false,zawrs=false,\
c=false,zifencei=false,zicsr=false,zihintntl=false,zihintpause=false,\
zbb=false,zba=false,zbs=false,zbc=false,zicbom=false,zicbop=false,\
zicboz=false
I've seen 4 different QEMU wrappers to handle arch string to QEMU CPU
option: 3 in-house scripts, 1 open source script in riscv-gnu-toolchain,
and I guess some vendors/developers may have their own scripts to do
that as well...
2. I don't know a better way other than reading the QEMU source code.
3. I don't really know the answer...
So how do other tools/simulators address these problems? Toolchains like
Clang and GCC use -march with an arch string to configure, and Spike uses
--isa=<ISA-string> to configure.
Could we introduce a similar way to configure QEMU? Yes, I think we can.
That's what this patch set does.
-cpu rv64,arch=<ISA-string>
to configure QEMU. And also introduce arch=help and arch=dump to show
which extensions are supported, and which extensions are enabled/disabled.
Also supported:
arch=<profile>["_"optional-ext]*
to specify configuration with RISC-V profiles like the toolchain convention[1].
[1]
https://github.com/riscv-non-isa/riscv-toolchain-conventions/blob/main/src/toolchain-conventions.adoc#specifying-the-target-profile-with--march
Overview
========
This patch series introduces the arch= CPU property for RISC-V, providing
a convenient interface to configure ISA extensions similar to GCC/Clang's
-march option.
The arch= property supports the following modes:
1. arch=dump
Print the current ISA configuration and exit. Shows the full ISA string
and the status of all supported extensions.
Example:
$ qemu-riscv64 -cpu rv64,v=true,arch=dump /bin/true
2. arch=help
Print a list of all supported ISA extensions and exit. Lists standard
single-letter extensions, multi-letter extensions, vendor extensions,
profiles, and vector length extensions.
Example:
$ qemu-riscv64 -cpu rv64,arch=help /bin/true
3. arch=<ISA-STRING>
Configure extensions using a standard RISC-V ISA string. The format is
rv{32|64}[single-letter-exts][_multi-letter-ext]*.
Key features:
- First extension must be i, e, or g (base ISA requirement)
- Single-letter extensions can be concatenated (rv64imafdc)
- Single-letter extensions can use underscore separators (rv64i_m_a_f_d_c)
- Multi-letter extensions are separated by underscores (_zba_zbb)
- Single-letter can transition directly to multi-letter (rv64imazba)
- Extensions i, e, g can only appear as the first extension
- When arch= is specified, all extensions are first reset to disabled
- G expands to imafd_zicsr_zifencei
- B expands to zba_zbb_zbs
Examples:
$ qemu-riscv64 -cpu rv64,arch=rv64gc_zba_zbb /bin/true
$ qemu-riscv64 -cpu rv64,arch=rv64imafdc_zba_zbb_zbc /bin/true
4. arch=<PROFILE>[_extension]*
Configure the CPU using a standard RISC-V profile, optionally with
additional extensions. Available profiles (64-bit only):
- rva22u64, rva22s64, rva23u64, rva23s64
Examples:
$ qemu-riscv64 -cpu rv64,arch=rva23u64 /bin/true
$ qemu-riscv64 -cpu rv64,arch=rva23u64_zbkb_zkne /bin/true
5. zvl*b extensions
Specify vector length (VLEN) in bits using zvl<N>b where N is a power
of 2 (32-65536). Requires v or zve* extension.
Examples:
$ qemu-riscv64 -cpu rv64,arch=rv64gcv_zvl256b /bin/true
$ qemu-riscv64 -cpu rv64,arch=rv64i_zve64f_zvl128b /bin/true
Individual extension properties (e.g., zba=true) can be combined with
arch= and will override the ISA string settings when specified after arch=.
Kito Cheng (5):
target/riscv: Add arch=dump CPU property for ISA introspection
target/riscv: Add arch=help to list supported ISA extensions
target/riscv: Add arch=ISA-STRING to configure extensions via ISA
string
target/riscv: Add arch=PROFILE to configure CPU using RISC-V profiles
target/riscv: Add zvl*b extension support in arch= property
docs/system/target-riscv.rst | 144 ++++++++
target/riscv/cpu.c | 226 ++++++++++++
target/riscv/cpu.h | 1 +
target/riscv/cpu_cfg_fields.h.inc | 3 +
target/riscv/tcg/tcg-cpu.c | 424 ++++++++++++++++++++++
tests/functional/riscv32/meson.build | 4 +
tests/functional/riscv32/test_cpu_arch.py | 94 +++++
tests/functional/riscv64/meson.build | 4 +
tests/functional/riscv64/test_cpu_arch.py | 411 +++++++++++++++++++++
9 files changed, 1311 insertions(+)
create mode 100644 tests/functional/riscv32/test_cpu_arch.py
create mode 100644 tests/functional/riscv64/test_cpu_arch.py
--
2.52.0
