According to the ISA spec of Zvfofp8min extension, "The Zvfofp8min extension requires on the Zve32f extension."
Signed-off-by: Max Chou <[email protected]> --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ target/riscv/vector_helper.c | 3 ++- 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8eab992154..b4b10b52d8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvfofp8min, PRIV_VERSION_1_12_0, ext_zvfofp8min), ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), @@ -778,6 +779,13 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) set_default_nan_mode(1, &env->fp_status); /* Default NaN value: sign bit clear, frac msb set */ set_float_default_nan_pattern(0b01000000, &env->fp_status); + /* + * RISC-V Zvfofp8min extension requires: + * - Same canonical NaN (0x7F) for both E4M3 and E5M2 formats + * - E5M2 format does not generate signaling NaNs (all NaNs are quiet) + */ + set_ocp_fp8_same_canonical_nan(true, &env->fp_status); + set_ocp_fp8e5m2_no_signal_nan(true, &env->fp_status); env->vill = true; #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index 3696f02ee0..59302894af 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -104,6 +104,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_zvfofp8min) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) BOOL_FIELD(ext_smctr) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 378b298886..ba89436f13 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -710,6 +710,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvfofp8min && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfofp8min extension depends on Zve32f extension"); + return; + } + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { error_setg(errp, "Zvfh extensions requires Zfhmin extension"); return; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ec0ea4c143..ee5a1e595b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -38,7 +38,8 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype) int xlen = riscv_cpu_xlen(env); target_ulong reserved = 0; - if (riscv_cpu_cfg(env)->ext_zvfbfa) { + if (riscv_cpu_cfg(env)->ext_zvfbfa || + riscv_cpu_cfg(env)->ext_zvfofp8min) { reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, xlen - 1 - R_VTYPE_RESERVED_SHIFT); } else { -- 2.43.7
