On 8. 1. 26. 16:31, Philippe Mathieu-Daudé wrote: > CAUTION: This email originated from outside of the organization. Do > not click links or open attachments unless you recognize the sender > and know the content is safe. > > > On 8/1/26 14:41, Djordje Todorovic wrote: >> Rebased again on top of very latest master branch by resolving >> build issues occured due to the changes in the code organization. > > I'm sorry for the unfortunate workflow pain you had with this series :( > No problem. :) It is part of journey. :)
>> Djordje Todorovic (12): >> target/riscv: Add cpu_set_exception_base >> target/riscv: Add MIPS P8700 CPU >> target/riscv: Add MIPS P8700 CSRs >> target/riscv: Add mips.ccmov instruction >> target/riscv: Add mips.pref instruction >> target/riscv: Add Xmipslsp instructions >> hw/misc: Add RISC-V CMGCR device implementation >> hw/misc: Add RISC-V CPC device implementation >> hw/riscv: Add support for RISCV CPS >> hw/riscv: Add support for MIPS Boston-aia board mode >> riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 >> test/functional: Add test for boston-aia board >
