On 1/8/26 22:14, Thomas Huth wrote:
On 08/01/2026 06.29, Richard Henderson wrote:
We now only support 64-bit code generation.
Signed-off-by: Richard Henderson <[email protected]>
---
tcg/i386/tcg-target-has.h | 8 +-
tcg/i386/tcg-target-reg-bits.h | 2 +-
tcg/i386/tcg-target.h | 13 +-
tcg/i386/tcg-target.c.inc | 552 ++++++---------------------------
4 files changed, 97 insertions(+), 478 deletions(-)
....
@@ -152,26 +127,13 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int
slot)
#define TCG_CT_CONST_TST 0x1000
#define TCG_CT_CONST_ZERO 0x2000
-/* Registers used with L constraint, which are the first argument
- registers on x86_64, and two random call clobbered registers on
- i386. */
-#if TCG_TARGET_REG_BITS == 64
-# define TCG_REG_L0 tcg_target_call_iarg_regs[0]
-# define TCG_REG_L1 tcg_target_call_iarg_regs[1]
-#else
-# define TCG_REG_L0 TCG_REG_EAX
-# define TCG_REG_L1 TCG_REG_EDX
-#endif
+/* Registers used with L constraint. */
+#define TCG_REG_L0 TCG_REG_EAX
+#define TCG_REG_L1 TCG_REG_EDX
I just want to double-check: This change looks confusing, since you kept the "else"
part ... but the (removed) comment indicated that this was the original intention? So this
is also bug fix?
It was unintentional, for sure.
I suspect that the (relatively) recent rewrite of tcg_out_qemu_{ld,st}_slow_path must have
hidden this change, by automatically adding the extra moves required to get the values
into the argument registers.
I'll double-check what's going on here...
r~
