This patchset introduces cache enumeration and a vCPU model for the Zhaoxin "Shijidadao" architecture. The model provides two variants via version aliases: Shijidadao-Server (v1) and Shijidadao-Client (v2). With these additions, QEMU can expose the core identity and features of this architecture without relying on host-passthrough.
--- Changes Since v1: - Incorporated Zhao Liu's suggested patch that introduces the cpuid_0x1f option. - Dropped explicit x-force-cpuid-0x1f property declarations from both Shijidadao-Server and Shijidadao-Client models, since the new option provides a cleaner solution. - Updated commit messages for the Client and Server patches to remove references to the earlier x-force-cpuid-0x1f approach. Changes Since v2: - Removed Zhao Liu's cpuid_0x1f patch from this series, as it has been merged into mainline (commit 3d4978). - Consolidated Shijidadao-Client and Shijidadao-Server into a single CPU model, differentiating them via version numbers and aliases. - Dropped the original Client v1 model, as it represents an early silicon revision rather than the final production version. - Updated the missing feature comment for FEAT_C000_0001_EDX to explicitly list individual features instead of using a generic TODO message. --- Ewan Hai (3): target/i386: Add cache model for Zhaoxin Shijidadao vCPUs target/i386: Introduce Zhaoxin Shijidadao CPU model target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model target/i386/cpu.c | 252 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 250 insertions(+), 2 deletions(-) -- 2.34.1
