From: Alistair Francis <[email protected]> The following changes since commit 3b5fe75e2c30e249acabe29924385782014c7632:
Merge tag 'pull-monitor-2026-01-07' of https://repo.or.cz/qemu/armbru into staging (2026-01-08 17:45:15 +1100) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260109 for you to fetch changes up to e71111e26bdf5e98243d6a896c9e595e205dd9bb: test/functional: Add test for boston-aia board (2026-01-09 15:14:58 +1000) ---------------------------------------------------------------- First RISC-V PR for 11. * Remove unused import statement from sifive_u test * Free allocated memory in core/loader * Add all available CSRs to 'info registers' * Add 'riscv-aia' accel prop info to documentation * Fix IOMMU MemoryRegion owner * Make riscv cpu.h target partially independent * Expand AIA target[i] source handling and refactor related code * Don't look up DDT cache in Off and Bare modes * Add Zilsd and Zclsd extension support * Add RISCV ZALASR extension * Add support for MIPS P8700 CPU ---------------------------------------------------------------- Akihiko Odaki (1): hw/riscv/riscv-iommu: Fix MemoryRegion owner Alistair Francis (4): hw/core/loader: Fixup whitespace for get_image_size() hw/core/loader: Free the image file descriptor on error hw/core/loader: Free the allocated string from size_to_str() target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val Anton Johansson (7): target/riscv: Fix size of trivial CPUArchState fields target/riscv: Fix size of mhartid target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read target/riscv: Combine mhpmevent and mhpmeventh target/riscv: Combine mcyclecfg and mcyclecfgh target/riscv: Combine minstretcfg and minstretcfgh target/riscv: Combine mhpmcounter and mhpmcounterh Daniel Henrique Barboza (4): target/riscv/cpu: add riscv_dump_csr() helper target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state() target/riscv: print all available CSRs in riscv_cpu_dump_state() docs/specs/riscv-aia.rst: add 'riscv-aia' accel prop info Djordje Todorovic (12): target/riscv: Add cpu_set_exception_base target/riscv: Add MIPS P8700 CPU target/riscv: Add MIPS P8700 CSRs target/riscv: Add mips.ccmov instruction target/riscv: Add mips.pref instruction target/riscv: Add Xmipslsp instructions hw/misc: Add RISC-V CMGCR device implementation hw/misc: Add RISC-V CPC device implementation hw/riscv: Add support for RISCV CPS hw/riscv: Add support for MIPS Boston-aia board mode riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 test/functional: Add test for boston-aia board Frank Chang (1): hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes Nikita Novikov (2): hw/intc/riscv_aplic: Expand inactive source handling for AIA target[i] hw/intc/riscv_aplic: Factor out source_active() and remove duplicate checks Roan Richmond (1): Add RISCV ZALASR extension Thomas Huth (1): tests/functional/riscv64/test_sifive_u: Remove unused import statement lxx (1): target/riscv: Add Zilsd and Zclsd extension support docs/specs/riscv-aia.rst | 43 ++- docs/system/riscv/mips.rst | 20 ++ docs/system/target-riscv.rst | 1 + configs/devices/riscv64-softmmu/default.mak | 1 + include/hw/misc/riscv_cmgcr.h | 48 +++ include/hw/misc/riscv_cpc.h | 64 ++++ include/hw/riscv/cps.h | 66 ++++ target/riscv/cpu-qom.h | 1 + target/riscv/cpu.h | 115 +++---- target/riscv/cpu_cfg.h | 5 + target/riscv/cpu_vendorid.h | 1 + target/riscv/cpu_cfg_fields.h.inc | 6 + target/riscv/insn16.decode | 8 + target/riscv/insn32.decode | 22 +- target/riscv/xmips.decode | 35 ++ hw/core/loader.c | 15 +- hw/intc/riscv_aplic.c | 66 ++-- hw/misc/riscv_cmgcr.c | 243 ++++++++++++++ hw/misc/riscv_cpc.c | 265 +++++++++++++++ hw/riscv/boston-aia.c | 476 +++++++++++++++++++++++++++ hw/riscv/cps.c | 196 +++++++++++ hw/riscv/riscv-iommu.c | 15 +- target/riscv/cpu.c | 157 +++++---- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 239 +++++++------- target/riscv/machine.c | 99 +++--- target/riscv/mips_csr.c | 217 ++++++++++++ target/riscv/pmu.c | 150 ++------- target/riscv/tcg/tcg-cpu.c | 35 +- target/riscv/translate.c | 5 + target/riscv/insn_trans/trans_rvzalasr.c.inc | 113 +++++++ target/riscv/insn_trans/trans_xmips.c.inc | 136 ++++++++ target/riscv/insn_trans/trans_zilsd.c.inc | 105 ++++++ hw/misc/Kconfig | 17 + hw/misc/meson.build | 3 + hw/riscv/Kconfig | 6 + hw/riscv/meson.build | 3 + target/riscv/meson.build | 2 + tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_boston.py | 123 +++++++ tests/functional/riscv64/test_sifive_u.py | 1 - 41 files changed, 2657 insertions(+), 470 deletions(-) create mode 100644 docs/system/riscv/mips.rst create mode 100644 include/hw/misc/riscv_cmgcr.h create mode 100644 include/hw/misc/riscv_cpc.h create mode 100644 include/hw/riscv/cps.h create mode 100644 target/riscv/xmips.decode create mode 100644 hw/misc/riscv_cmgcr.c create mode 100644 hw/misc/riscv_cpc.c create mode 100644 hw/riscv/boston-aia.c create mode 100644 hw/riscv/cps.c create mode 100644 target/riscv/mips_csr.c create mode 100644 target/riscv/insn_trans/trans_rvzalasr.c.inc create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc create mode 100755 tests/functional/riscv64/test_boston.py
