On 1/9/26 17:54, [email protected] wrote:
From: Alistair Francis<[email protected]>
The following changes since commit 3b5fe75e2c30e249acabe29924385782014c7632:
Merge tag 'pull-monitor-2026-01-07' ofhttps://repo.or.cz/qemu/armbru into
staging (2026-01-08 17:45:15 +1100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260109
for you to fetch changes up to e71111e26bdf5e98243d6a896c9e595e205dd9bb:
test/functional: Add test for boston-aia board (2026-01-09 15:14:58 +1000)
----------------------------------------------------------------
First RISC-V PR for 11.
* Remove unused import statement from sifive_u test
* Free allocated memory in core/loader
* Add all available CSRs to 'info registers'
* Add 'riscv-aia' accel prop info to documentation
* Fix IOMMU MemoryRegion owner
* Make riscv cpu.h target partially independent
* Expand AIA target[i] source handling and refactor related code
* Don't look up DDT cache in Off and Bare modes
* Add Zilsd and Zclsd extension support
* Add RISCV ZALASR extension
* Add support for MIPS P8700 CPU
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/11.0 as
appropriate.
r~
