On Sat, Jan 10, 2026 at 12:42 AM Joel Stanley <[email protected]> wrote: > > JEP106 has two vendor IDs for Tenstorrent. We will use Bank 16, hex 0xa1: > > ((16 - 1) << 7) | (0xa1 & ~0x80) = 0x7a1
The value LGTM, it matches JEP106BM, and matches the Tenstorrent documentation I have. I would probably say that it's company 33. Which is 0xa1 with the parity bit added, but the parity bit isn't used in the calculation, ie: ((16 - 1) << 7) | 33 = 0x7a1 Mentioning that it's company 33 (0x21) would make it a little easier to match it up with other public sources, eg openocd: https://github.com/openocd-org/openocd/blob/1ebff3ab33c77e3f8fb4e1ddda262b606b572af1/src/helper/jep106.inc#L1935 > Add it to the Ascalon CPU definition as the mvendorid CSR. > > Signed-off-by: Joel Stanley <[email protected]> Reviewed-by: Michael Ellerman <[email protected]> cheers > diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h > index f1ffc66542a0..751a13aace47 100644 > --- a/target/riscv/cpu_vendorid.h > +++ b/target/riscv/cpu_vendorid.h > @@ -8,4 +8,6 @@ > #define VEYRON_V1_MIMPID 0x111 > #define VEYRON_V1_MVENDORID 0x61f > > +#define TENSTORRENT_VENDOR_ID 0x7a1 > + > #endif /* TARGET_RISCV_CPU_VENDORID_H */ > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index efdec49e49ed..85ce4d83a371 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3190,6 +3190,8 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.ext_svnapot = true, > .cfg.ext_svpbmt = true, > > + .cfg.mvendorid = TENSTORRENT_VENDOR_ID, > + > .cfg.max_satp_mode = VM_1_10_SV57, > ), > > -- > 2.47.3 >
