MemLog::width is a uint8_t value mapped to a TCGv (32 bit), the only reason this currently works is because MemLog::width is padded to 32 bits. Widen the field to uint32_t and fix the size of the TCGv operations as well. Use uint32_t when referencing and passing around the field, as valid values are asserted in commit_store().
Signed-off-by: Anton Johansson <[email protected]> -- Changes in v2: - Removed truncation to uint8_t, valid values of 1,2,4,8 are checked in commit_store() already. --- target/hexagon/cpu.h | 2 +- target/hexagon/genptr.h | 2 +- target/hexagon/op_helper.h | 4 ++-- target/hexagon/translate.h | 2 +- target/hexagon/genptr.c | 6 +++--- target/hexagon/op_helper.c | 8 ++++---- target/hexagon/translate.c | 4 ++-- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 656b7dc044..85afd59277 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -46,7 +46,7 @@ typedef struct { target_ulong va; - uint8_t width; + uint32_t width; uint32_t data32; uint64_t data64; } MemLog; diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 228d7f1d7d..45ee038ca9 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -24,7 +24,7 @@ extern const SemanticInsn opcode_genptr[]; -void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot); +void gen_store32(TCGv vaddr, TCGv src, uint32_t width, uint32_t slot); void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h index 66119cf3d4..e8fdabddb3 100644 --- a/target/hexagon/op_helper.h +++ b/target/hexagon/op_helper.h @@ -20,8 +20,8 @@ /* Misc functions */ void log_store64(CPUHexagonState *env, target_ulong addr, - int64_t val, int width, int slot); + int64_t val, uint32_t width, int slot); void log_store32(CPUHexagonState *env, target_ulong addr, - target_ulong val, int width, int slot); + target_ulong val, uint32_t width, int slot); #endif diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index a0102b6cbd..b37cb49238 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -272,7 +272,7 @@ extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_slot_cancelled; extern TCGv hex_new_value_usr; extern TCGv hex_store_addr[STORES_MAX]; -extern TCGv hex_store_width[STORES_MAX]; +extern TCGv_i32 hex_store_width[STORES_MAX]; extern TCGv hex_store_val32[STORES_MAX]; extern TCGv_i64 hex_store_val64[STORES_MAX]; extern TCGv hex_llsc_addr; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 36968549d5..9eb21da6f3 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -387,10 +387,10 @@ static TCGv gen_slotval(DisasContext *ctx) } #endif -void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot) +void gen_store32(TCGv vaddr, TCGv src, uint32_t width, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); - tcg_gen_movi_tl(hex_store_width[slot], width); + tcg_gen_movi_i32(hex_store_width[slot], width); tcg_gen_mov_tl(hex_store_val32[slot], src); } @@ -430,7 +430,7 @@ void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot) void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); - tcg_gen_movi_tl(hex_store_width[slot], 8); + tcg_gen_movi_i32(hex_store_width[slot], 8); tcg_gen_mov_i64(hex_store_val64[slot], src); } diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 554e7dd447..9375ce3aff 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -52,7 +52,7 @@ G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp) } void log_store32(CPUHexagonState *env, target_ulong addr, - target_ulong val, int width, int slot) + target_ulong val, uint32_t width, int slot) { env->mem_log_stores[slot].va = addr; env->mem_log_stores[slot].width = width; @@ -60,7 +60,7 @@ void log_store32(CPUHexagonState *env, target_ulong addr, } void log_store64(CPUHexagonState *env, target_ulong addr, - int64_t val, int width, int slot) + int64_t val, uint32_t width, int slot) { env->mem_log_stores[slot].va = addr; env->mem_log_stores[slot].width = width; @@ -69,7 +69,7 @@ void log_store64(CPUHexagonState *env, target_ulong addr, static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra) { - uint8_t width = env->mem_log_stores[slot_num].width; + uint32_t width = env->mem_log_stores[slot_num].width; target_ulong va = env->mem_log_stores[slot_num].va; switch (width) { @@ -363,7 +363,7 @@ static void probe_store(CPUHexagonState *env, int slot, int mmu_idx, bool is_predicated, uintptr_t retaddr) { if (!is_predicated || !(env->slot_cancelled & (1 << slot))) { - size1u_t width = env->mem_log_stores[slot].width; + uint32_t width = env->mem_log_stores[slot].width; target_ulong va = env->mem_log_stores[slot].va; probe_write(env, va, width, mmu_idx, retaddr); } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 3762faec4d..830748602a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -55,7 +55,7 @@ TCGv hex_pred[NUM_PREGS]; TCGv hex_slot_cancelled; TCGv hex_new_value_usr; TCGv hex_store_addr[STORES_MAX]; -TCGv hex_store_width[STORES_MAX]; +TCGv_i32 hex_store_width[STORES_MAX]; TCGv hex_store_val32[STORES_MAX]; TCGv_i64 hex_store_val64[STORES_MAX]; TCGv hex_llsc_addr; @@ -1100,7 +1100,7 @@ void hexagon_translate_init(void) store_addr_names[i]); snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); - hex_store_width[i] = tcg_global_mem_new(tcg_env, + hex_store_width[i] = tcg_global_mem_new_i32(tcg_env, offsetof(CPUHexagonState, mem_log_stores[i].width), store_width_names[i]); -- 2.51.0
