When an mc/mc6 trigger triggers on a load/store and raises a breakpoint exception, put the matching memory address into tval, as is already done for exec addresses matching.
Tval for breakpoint exceptions is optional in the spec, but it seems more consistent to implement it for load/store if exec is implemented. Signed-off-by: Nicholas Piggin <[email protected]> --- target/riscv/debug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index bd61b7ff02..19c45fb13c 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -1075,6 +1075,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) if ((wp->flags & flags) && (wp->vaddr == addr)) { if (do_trigger_action(env, i)) { + env->badaddr = wp->vaddr; return true; } } @@ -1093,6 +1094,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) if ((wp->flags & flags) && (wp->vaddr == addr)) { if (do_trigger_action(env, i)) { + env->badaddr = wp->vaddr; return true; } } -- 2.51.0
