Re: [PATCH] target/arm: Implement WFE, SEV and SEVONPEND for Cortex-M

[Ashish Anand]

It looks like there's a missing piece here: R_BPBR in the v8M
Arm ARM says that the event register is also set on exception
entry and exception return.

You're right that I'm missing this. Looking at DDI0403E_B & DDI0419E (ARMv7-M & ARMv6-M) 
Section B1.5.18:
- "An asynchronous exception at a priority that preempts any currently 
  active exception" is a WFE wakeup event
- "Any WFE wakeup event, or the execution of an exception return instruction, sets the Event Register"  

So does this imply that even in ARMv7-M/ARMv6-M (not just ARMv8-M), the event register should 
be set on:
1. Exception entry (when exception is taken/preempts)
2. Exception return

Why do we need to do this tcg_gen_exit_tb() and set DISAS_NORETURN ?

Do we even need to end the current TB on a SEV instruction ?


You're absolutely right - SEV doesn't need to end the TB. It just sets 
the event register. I'll remove the tcg_gen_exit_tb() and DISAS_NORETURN.


         case DISAS_WFE:
             gen_helper_wfe(tcg_env);
+            tcg_gen_exit_tb(NULL, 0);

Why is this necessary ?


I think this is necessary because helper_wfe() can conditionally return (when 
event register is set), following the same pattern as WFI.

WFI helper can return if cpu_has_work(), so it needs tcg_gen_exit_tb() 
for that return path. WFE helper can return if event_register is set, 
so it also needs tcg_gen_exit_tb() for that return path


Thanks,
Ashish