Jonathan Cameron <[email protected]> writes:
> From: Shiju Jose <[email protected]>
>
> CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
> has updated with following new fields.
> 1. Component Identifier
> 2. Sub-channel of the memory event location
> 3. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 4. Corrected Volatile Memory Error Count at Event
> 5. Memory Event Sub-Type
>
> Add updates for the above spec changes in the CXL DRAM event
> reporting and QMP command to inject DRAM event.
>
> In order to ensure consistency update all specification references
> for this command to CXL r3.2.
>
> Signed-off-by: Shiju Jose <[email protected]>
> Signed-off-by: Jonathan Cameron <[email protected]>
> ---
> v3: Update all spec references for this command to 3.2 for consistency
> (Markus)
> ---
> qapi/cxl.json | 31 +++++++++++++++++++++------
> include/hw/cxl/cxl_events.h | 9 ++++++--
> hw/mem/cxl_type3.c | 42 +++++++++++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 7 +++++++
> 4 files changed, 81 insertions(+), 8 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index c159687f849c..630c37d64eed 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -131,21 +131,21 @@
> ##
> # @CXLDRAMEvent:
> #
> -# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> +# Event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2).
> #
> # @dpa: Device Physical Address (relative to @path device). Note
> -# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
> +# lower bits include some flags. See CXL r3.2 Table 8-58 DRAM
> # Event Record, Physical Address.
> #
> # @descriptor: Memory Event Descriptor with additional memory event
> -# information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory
> +# information. See CXL r3.2 Table 8-58 DRAM Event Record, Memory
> # Event Descriptor for bit definitions.
> #
> -# @type: Type of memory event that occurred. See CXL r3.0 Table 8-44
> +# @type: Type of memory event that occurred. See CXL r3.2 Table 8-58
> # DRAM Event Record, Memory Event Type for possible values.
> #
> # @transaction-type: Type of first transaction that caused the event
> -# to occur. See CXL r3.0 Table 8-44 DRAM Event Record,
> +# to occur. See CXL r3.2 Table 8-58 DRAM Event Record,
> # Transaction Type for possible values.
> #
> # @channel: The channel of the memory event location. A channel is an
> @@ -169,6 +169,21 @@
> # @correction-mask: Bits within each nibble. Used in order of bits
> # set in the nibble-mask. Up to 4 nibbles may be covered.
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
> +#
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @sub-channel: The sub-channel of the memory event location.
> +#
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +# threshold event flags.
> +#
> +# @cvme-count: Corrected volatile memory error count at event.
> +#
> +# @sub-type: Memory event sub-type.
> +#
> # Since: 8.1
> ##
> { 'struct': 'CXLDRAMEvent',
> @@ -177,7 +192,11 @@
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> - '*column': 'uint16', '*correction-mask': [ 'uint64' ]
> + '*column': 'uint16', '*correction-mask': [ 'uint64' ],
> + '*component-id': 'str', '*is-comp-id-pldm':'bool',
> + '*sub-channel':'uint8',
> + '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
> + 'sub-type':'uint8'
> }}
>
> ##
# @cxl-inject-dram-event:
#
# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
Should we update this reference as well?
# This event type is reported via one of the event logs
# specified via the log parameter.
#
# Since: 8.1
##
{ 'command': 'cxl-inject-dram-event',
'data': 'CXLDRAMEvent' }
[...]
