Starting from M4 cores and MacOS 15.2 SDK, HVF can virtualise FEAT_SME2.
Reviewed-by: Mohamed Mediouni <[email protected]>
Signed-off-by: Manos Pitsidianakis <[email protected]>
---
target/arm/cpu.c | 4 +++-
target/arm/cpu64.c | 13 ++++++++++++-
target/arm/hvf/hvf.c | 25 +++++++++++++------------
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index
caf7980b1fc5244c5c2f130e79ba869456c20c88..7f4ebfdf61217db6075495119c1b642bc2abf295
100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1577,7 +1577,9 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
* assumes it, so if the user asked for sve=off then turn off SME also.
* (KVM doesn't currently support SME at all.)
*/
- if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve,
cpu)) {
+ if (!hvf_enabled()
+ && cpu_isar_feature(aa64_sme, cpu)
+ && !cpu_isar_feature(aa64_sve, cpu)) {
object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort);
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
bf303813701972648fa6751ffe352ba074ca6442..8dd9eb46c783a799a53891a6ddad40b930e95eb4
100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -329,9 +329,20 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
{
uint32_t vq_map = cpu->sme_vq.map;
uint32_t vq_init = cpu->sme_vq.init;
- uint32_t vq_supported = cpu->sme_vq.supported;
+ uint32_t vq_supported;
uint32_t vq;
+ if (hvf_enabled()) {
+ if (hvf_arm_sme2_supported()) {
+ vq_supported = hvf_arm_sme2_get_svl();
+ } else {
+ assert(!cpu_isar_feature(aa64_sme, cpu));
+ vq_supported = 0;
+ }
+ } else {
+ vq_supported = cpu->sme_vq.supported;
+ }
+
if (vq_map == 0) {
if (!cpu_isar_feature(aa64_sme, cpu)) {
SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0);
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index
6c5061742862635ae394f764188114f939259703..01bbb90b962156885021da75a0d62ae3c39ff5b0
100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1043,18 +1043,18 @@ static bool
hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);
- /*
- * Disable SME, which is not properly handled by QEMU hvf yet.
- * To allow this through we would need to:
- * - make sure that the SME state is correctly handled in the
- * get_registers/put_registers functions
- * - get the SME-specific CPU properties to work with accelerators
- * other than TCG
- * - fix any assumptions we made that SME implies SVE (since
- * on the M4 there is SME but not SVE)
- */
- SET_IDREG(&host_isar, ID_AA64PFR1,
- GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK);
+ if (hvf_arm_sme2_supported()) {
+ t = GET_IDREG(&host_isar, ID_AA64PFR1);
+ t = FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */
+ SET_IDREG(&host_isar, ID_AA64PFR1, t);
+
+ t = GET_IDREG(&host_isar, ID_AA64SMFR0);
+ t = FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 1); /* FEAT_SME2 */
+ SET_IDREG(&host_isar, ID_AA64SMFR0, t);
+ } else {
+ SET_IDREG(&host_isar, ID_AA64PFR1,
+ GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK);
+ }
ahcf->isar = host_isar;
@@ -1252,6 +1252,7 @@ int hvf_arch_init_vcpu(CPUState *cpu)
arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]);
assert_hvf_ok(ret);
+ aarch64_add_sme_properties(OBJECT(cpu));
return 0;
}
--
2.47.3
