From: Bernhard Beschow <[email protected]>
This reverts commit 1e76667f7adf48c6c3596aaa26b8886b57b8498d.
Unaware that the constants were named after Linux and U-Boot code,
commit 1e76667f7adf ("hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*")
changed the naming to be consistent with the function names. Fix the
constant naming to be consistent with Linux and U-Boot again. In the
next step, the function names will be renamed according to Linux and
U-Boot code as well.
Signed-off-by: Bernhard Beschow <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: BALATON Zoltan <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
---
hw/sd/sdhci.c | 66 +++++++++++++++++++++++++--------------------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 23d8f7cbc8d..ccdfc59af85 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1639,24 +1639,24 @@ static void sdhci_bus_class_init(ObjectClass *klass,
const void *data)
/* --- qdev i.MX eSDHC --- */
-#define USDHC_MIX_CTRL 0x48
+#define ESDHC_MIX_CTRL 0x48
-#define USDHC_VENDOR_SPEC 0xc0
-#define USDHC_IMX_FRC_SDCLK_ON (1 << 8)
+#define ESDHC_VENDOR_SPEC 0xc0
+#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8)
-#define USDHC_DLL_CTRL 0x60
+#define ESDHC_DLL_CTRL 0x60
-#define USDHC_TUNING_CTRL 0xcc
-#define USDHC_TUNE_CTRL_STATUS 0x68
-#define USDHC_WTMK_LVL 0x44
+#define ESDHC_TUNING_CTRL 0xcc
+#define ESDHC_TUNE_CTRL_STATUS 0x68
+#define ESDHC_WTMK_LVL 0x44
/* Undocumented register used by guests working around erratum ERR004536 */
-#define USDHC_UNDOCUMENTED_REG27 0x6c
+#define ESDHC_UNDOCUMENTED_REG27 0x6c
-#define USDHC_CTRL_4BITBUS (0x1 << 1)
-#define USDHC_CTRL_8BITBUS (0x2 << 1)
+#define ESDHC_CTRL_4BITBUS (0x1 << 1)
+#define ESDHC_CTRL_8BITBUS (0x2 << 1)
-#define USDHC_PRNSTS_SDSTB (1 << 3)
+#define ESDHC_PRNSTS_SDSTB (1 << 3)
static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
{
@@ -1677,11 +1677,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset,
unsigned size)
hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
- hostctl1 |= USDHC_CTRL_8BITBUS;
+ hostctl1 |= ESDHC_CTRL_8BITBUS;
}
if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
- hostctl1 |= USDHC_CTRL_4BITBUS;
+ hostctl1 |= ESDHC_CTRL_4BITBUS;
}
ret = hostctl1;
@@ -1692,21 +1692,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset,
unsigned size)
case SDHC_PRNSTS:
/* Add SDSTB (SD Clock Stable) bit to PRNSTS */
- ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
+ ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
- ret |= USDHC_PRNSTS_SDSTB;
+ ret |= ESDHC_PRNSTS_SDSTB;
}
break;
- case USDHC_VENDOR_SPEC:
+ case ESDHC_VENDOR_SPEC:
ret = s->vendor_spec;
break;
- case USDHC_DLL_CTRL:
- case USDHC_TUNE_CTRL_STATUS:
- case USDHC_UNDOCUMENTED_REG27:
- case USDHC_TUNING_CTRL:
- case USDHC_MIX_CTRL:
- case USDHC_WTMK_LVL:
+ case ESDHC_DLL_CTRL:
+ case ESDHC_TUNE_CTRL_STATUS:
+ case ESDHC_UNDOCUMENTED_REG27:
+ case ESDHC_TUNING_CTRL:
+ case ESDHC_MIX_CTRL:
+ case ESDHC_WTMK_LVL:
ret = 0;
break;
}
@@ -1722,16 +1722,16 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
uint32_t value = (uint32_t)val;
switch (offset) {
- case USDHC_DLL_CTRL:
- case USDHC_TUNE_CTRL_STATUS:
- case USDHC_UNDOCUMENTED_REG27:
- case USDHC_TUNING_CTRL:
- case USDHC_WTMK_LVL:
+ case ESDHC_DLL_CTRL:
+ case ESDHC_TUNE_CTRL_STATUS:
+ case ESDHC_UNDOCUMENTED_REG27:
+ case ESDHC_TUNING_CTRL:
+ case ESDHC_WTMK_LVL:
break;
- case USDHC_VENDOR_SPEC:
+ case ESDHC_VENDOR_SPEC:
s->vendor_spec = value;
- if (value & USDHC_IMX_FRC_SDCLK_ON) {
+ if (value & ESDHC_IMX_FRC_SDCLK_ON) {
s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
} else {
s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
@@ -1796,12 +1796,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
* Second, split "Data Transfer Width" from bits 2 and 1 in to
* bits 5 and 1
*/
- if (value & USDHC_CTRL_8BITBUS) {
+ if (value & ESDHC_CTRL_8BITBUS) {
hostctl1 |= SDHC_CTRL_8BITBUS;
}
- if (value & USDHC_CTRL_4BITBUS) {
- hostctl1 |= USDHC_CTRL_4BITBUS;
+ if (value & ESDHC_CTRL_4BITBUS) {
+ hostctl1 |= ESDHC_CTRL_4BITBUS;
}
/*
@@ -1824,7 +1824,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
sdhci_write(opaque, offset, value, size);
break;
- case USDHC_MIX_CTRL:
+ case ESDHC_MIX_CTRL:
/*
* So, when SD/MMC stack in Linux tries to write to "Transfer
* Mode Register", ESDHC i.MX quirk code will translate it
--
2.52.0
