On 1/18/2026 5:47 PM, Mi, Dapeng wrote:
>
> On 1/17/2026 9:10 AM, Zide Chen wrote:
>> BTS (Branch Trace Store), enumerated by IA32_MISC_ENABLE.BTS_UNAVAILABLE
>> (bit 11), is deprecated and has been superseded by LBR and Intel PT.
>>
>> KVM yields control of the above mentioned bit to userspace since KVM
>> commit 9fc222967a39 ("KVM: x86: Give host userspace full control of
>> MSR_IA32_MISC_ENABLES").
>>
>> However, QEMU does not set this bit, which allows guests to write the
>> BTS and BTINT bits in IA32_DEBUGCTL. Since KVM doesn't support BTS,
>> this may lead to unexpected MSR access errors.
>>
>> Setting this bit does not introduce migration compatibility issues, so
>> the VMState version_id is not bumped.
>>
>> Signed-off-by: Zide Chen <[email protected]>
>> ---
>> target/i386/cpu.h | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index 2bbc977d9088..f2b79a8bf1dc 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -474,7 +474,10 @@ typedef enum X86Seg {
>>
>> #define MSR_IA32_MISC_ENABLE 0x1a0
>> /* Indicates good rep/movs microcode on some processors: */
>> -#define MSR_IA32_MISC_ENABLE_DEFAULT 1
>> +#define MSR_IA32_MISC_ENABLE_FASTSTRING 1
>
> To keep the same code style and make users clearly know the macro is a
> bitmask, better define MSR_IA32_MISC_ENABLE_FASTSTRING like below.
>
> #define MSR_IA32_MISC_ENABLE_FASTSTRING (1ULL << 0)
Yes. Thanks.
>
>> +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
>> +#define MSR_IA32_MISC_ENABLE_DEFAULT (MSR_IA32_MISC_ENABLE_FASTSTRING
>> |\
>> +
>> MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
>
> Better move the macro "MSR_IA32_MISC_ENABLE_DEFAULT" after
> "MSR_IA32_MISC_ENABLE_MWAIT".
>
Thanks. Will do.
>> #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
>>
>> #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
