According to RVV Spec Section 3.4.2, the correct constraint for fractional LMUL is `SEWMIN <= sew <= LMUL * ELEN`, not `SEWMIN <= sew <= LMUL * VLEN`.
When parsing the instructions `vsetivli zero, 2, e64, mf2, ta, mu; vmv.s.x v24, s3` with riscv_zve64x, an illegal instruction exception should be reported but isn't. This patch fixes the issue. Signed-off-by: Zhijin Zeng <[email protected]> --- target/riscv/vector_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2de3358ee8..f0315629ec 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong reserved = s2 & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, xlen - 1 - R_VTYPE_RESERVED_SHIFT); - uint16_t vlen = cpu->cfg.vlenb << 3; int8_t lmul; if (vlmul & 4) { /* * Fractional LMUL, check: * - * VLEN * LMUL >= SEW - * VLEN >> (8 - lmul) >= sew - * (vlenb << 3) >> (8 - lmul) >= sew + * ELEN * LMUL >= SEW + * ELEN >> (8 - lmul) >= sew + * (cpu->cfg.elen) >> (8 - lmul) >= sew */ - if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) { + if (vlmul == 4 || (cpu->cfg.elen >> (8 - vlmul)) < sew) { vill = true; } } -- 2.43.0
