Hi Max, > But I think that the proposed fix of adding vext_check_isa_ill to whole > register load/store instructions will violate the RISC-V vector specification. > > With this patch, whole register load/store instructions would incorrectly > raise illegal instruction exceptions when vill=1, even though the V extension > is enabled.
You're entirely correct! I should probably have known or noticed that, oops. So to sum up: * The bug is that vs*r currently don't raise SIGILL when using a non-RVV CPU; * but vs*r.v not having a vill check is intended and not the cause; * instead the bug affects all instructions but the vill check just masks it for everyone except vs*r.v. > I would recommend that we should fix this bug at riscv_get_tb_cpu_state by > checking the CPU configuration in CONFIG_USER_ONLY block (user mode) to > ensures require_rvv returns false when the vector is disabled. I'll start from here and come back with a v2 that (hopefully) does the right thing. Sébastien
