Re: target/arm: Implement WFE, SEV and SEVONPEND for Cortex-M

[Ashish Anand]

I looked a bit more closely at the SEVONPEND language in the Arm ARM,
and it says
# When SCR.SEVONPEND bit associated with a security state is one, interrupts
# transitioning from the inactive to the pending state that target that
# security state are wakeup events.

So the thing that determines whether we are looking at the S or the NS
SCR.SEVONPEND is "does this interrupt target S or NS security state?".
We have a function for that:
exc_targets_secure(s, irq)

So we can determine which SCR to look at in this nvic_update_pending_state()
function and we don't need the callers to pass in scr_bank to us.

exc_targets_secure() requires it to be called only for a non-banked
exception, but we can call it only inside the irq >= NVIC_FIRST_IRQ
condition, as all interrupts are non-banked.

This should simplify the changes you're making at the callsites.

thanks
-- PMM


Hi Peter,

Thanks for the detailed review! You're absolutely right - determining 
scr_bank inside nvic_update_pending_state() using exc_targets_secure() 
is cleaner and removes the burden from all the callsites. I'll update 
this for v4.

Thanks,
Ashish