On Wed, Feb 04, 2026 at 02:59:59PM +0000, Alireza Sanaee wrote: > The CXL address to device decoding logic is complex because of the need > to correctly decode fine grained interleave. The current implementation > prevents use with KVM where executed instructions may reside in that > memory and gives very slow performance even in TCG. > > In many real cases non interleaved memory configurations are useful and > for those we can use a more conventional memory region alias allowing > similar performance to other memory in the system. > > Whether this fast path is applicable can be established once the full > set of HDM decoders has been committed (in whatever order the guest > decides to commit them). As such a check is performed on each commit / > uncommit of HDM decoder to establish if the alias should be added or > removed. >
Tested this on top of Jonathan's most recent draft branch, works nicely (with obvious fixups mentioned here). Has been working nicely. Tested-by: Gregory Price <[email protected]> ---- Jonathan the HACK patch was giving me issues with registers getting plopped in the middle of a CFMW, not sure if this is the right fix or not Fixes: 9a1b11bc03 hw/i386/pc: Add Aspeed i2c controller + MCTP with ACPI table diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f9d0bb3b41..9c244d40a7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -957,8 +957,8 @@ void pc_memory_init(PCMachineState *pcms, memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); memory_region_add_subregion(system_memory, cxl_base, mr); cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); - pcms->i2c_base = cxl_base + cxl_size - 0x4000; cxl_resv_end = cxl_fmws_set_memmap(cxl_base, maxphysaddr); + pcms->i2c_base = cxl_resv_end + 0x1000; cxl_fmws_update_mmio(); }
