On Fri, Feb 06, 2026 at 02:48:13PM +0000, Shameer Kolothum wrote:
> From: Nicolin Chen <[email protected]>
>
> Add support for allocating IOMMUFD hardware queues when VCMDQ base
> registers are programmed by the guest.
>
> When a VCMDQ BASE register is written with a valid RAM-backed address,
> allocate a corresponding IOMMUFD hardware queue for the CMDQV device.
Let's mention that this is because QEMU doesn't trap VCMDQ_EN bit,
which is a part of VCMDQ_CONFIG register accessed via the mmap'd
page0.
> +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index,
> + Error **errp)
> +{
> + SMMUv3AccelState *accel = cmdqv->s_accel;
> + uint64_t base_mask = (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK |
> + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32;
> + uint64_t addr = cmdqv->vcmdq_base[index] & base_mask;
> + uint64_t log2 = cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_MASK;
> + uint64_t size = 1ULL << (log2 + 4);
> + IOMMUFDHWqueue *vcmdq = cmdqv->vcmdq[index];
> + IOMMUFDViommu *viommu = accel->viommu;
> + IOMMUFDHWqueue *hw_queue;
> + uint32_t hw_queue_id;
> +
> + /* Ignore any invalid address. This may come as part of reset etc */
> + if (!address_space_is_ram(&address_space_memory, addr)) {
> + return true;
We should probably check addr and size - 1 + addr?
Nicolin
